Lines Matching refs:write_cpu_ctrl
242 write_cpu_ctrl(sc->config->bridge_irq_cause, irq_cause); in mv_timer_attach()
246 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); in mv_timer_attach()
276 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); in mv_hardclock()
391 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); in mv_watchdog_enable_armv5()
395 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); in mv_watchdog_enable_armv5()
399 write_cpu_ctrl(RSTOUTn_MASK, val); in mv_watchdog_enable_armv5()
413 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); in mv_watchdog_enable_armadaxp()
439 write_cpu_ctrl(RSTOUTn_MASK, val); in mv_watchdog_disable_armv5()
443 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); in mv_watchdog_disable_armv5()
447 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); in mv_watchdog_disable_armv5()
465 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); in mv_watchdog_disable_armadaxp()