990 #define MLX5_CAP_GEN(mdev, cap) \  argument
991 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
993 #define	MLX5_CAP_GEN_64(mdev, cap)					\  argument
994 	MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
996 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
997 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
999 #define MLX5_CAP_ETH(mdev, cap) \  argument
1001 		 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1003 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
1005 		 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1007 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1008 	MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1010 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1011 	MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1013 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1014 	MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1016 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1017 	MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1019 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1020 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1022 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
1023 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1025 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1026 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1028 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \  argument
1029 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1031 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1033 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1035 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
1037 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1039 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1040 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1042 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
1043 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1045 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1046 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1048 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1049 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1051 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1052 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1054 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1055 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1057 #define MLX5_CAP_ESW(mdev, cap) \  argument
1059 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1061 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1063 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1065 #define MLX5_CAP_ODP(mdev, cap)\  argument
1066 	MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1068 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1069 	MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1071 #define MLX5_CAP_SNAPSHOT(mdev, cap) \  argument
1073 		 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1075 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \  argument
1077 		 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1079 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \  argument
1081 		 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1083 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \  argument
1085 		 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1087 #define MLX5_CAP_DEBUG(mdev, cap) \  argument
1089 		 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1091 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \  argument
1093 		 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1095 #define MLX5_CAP_QOS(mdev, cap) \  argument
1097 		 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1099 #define MLX5_CAP_QOS_MAX(mdev, cap) \  argument
1101 		 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1103 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \  argument
1104 	MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1106 #define	MLX5_CAP_PCAM_REG(mdev, reg) \  argument
1107 	MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1109 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \  argument
1110 	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1112 #define	MLX5_CAP_MCAM_REG(mdev, reg) \  argument
1113 	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1115 #define	MLX5_CAP_QCAM_REG(mdev, fld) \  argument
1116 	MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1118 #define	MLX5_CAP_QCAM_FEATURE(mdev, fld) \  argument
1119 	MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1121 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1122 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1124 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1125 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1127 #define	MLX5_CAP_TLS(mdev, cap) \  argument
1128 	MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap)