26 	phy->ops.init_params = igc_null_ops_generic;  in igc_init_phy_ops_generic()
27 	phy->ops.acquire = igc_null_ops_generic;  in igc_init_phy_ops_generic()
28 	phy->ops.check_reset_block = igc_null_ops_generic;  in igc_init_phy_ops_generic()
29 	phy->ops.force_speed_duplex = igc_null_ops_generic;  in igc_init_phy_ops_generic()
30 	phy->ops.get_info = igc_null_ops_generic;  in igc_init_phy_ops_generic()
31 	phy->ops.set_page = igc_null_set_page;  in igc_init_phy_ops_generic()
32 	phy->ops.read_reg = igc_null_read_reg;  in igc_init_phy_ops_generic()
33 	phy->ops.read_reg_locked = igc_null_read_reg;  in igc_init_phy_ops_generic()
34 	phy->ops.read_reg_page = igc_null_read_reg;  in igc_init_phy_ops_generic()
35 	phy->ops.release = igc_null_phy_generic;  in igc_init_phy_ops_generic()
36 	phy->ops.reset = igc_null_ops_generic;  in igc_init_phy_ops_generic()
37 	phy->ops.set_d0_lplu_state = igc_null_lplu_state;  in igc_init_phy_ops_generic()
38 	phy->ops.set_d3_lplu_state = igc_null_lplu_state;  in igc_init_phy_ops_generic()
39 	phy->ops.write_reg = igc_null_write_reg;  in igc_init_phy_ops_generic()
40 	phy->ops.write_reg_locked = igc_null_write_reg;  in igc_init_phy_ops_generic()
41 	phy->ops.write_reg_page = igc_null_write_reg;  in igc_init_phy_ops_generic()
42 	phy->ops.power_up = igc_null_phy_generic;  in igc_init_phy_ops_generic()
43 	phy->ops.power_down = igc_null_phy_generic;  in igc_init_phy_ops_generic()
141 	if (!phy->ops.read_reg)  in igc_get_phy_id()
144 	ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);  in igc_get_phy_id()
150 	ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);  in igc_get_phy_id()
301 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);  in igc_phy_setup_autoneg()
307 		ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,  in igc_phy_setup_autoneg()
316 		ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<  in igc_phy_setup_autoneg()
444 	ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);  in igc_phy_setup_autoneg()
451 		ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,  in igc_phy_setup_autoneg()
456 		ret_val = phy->ops.write_reg(hw,  in igc_phy_setup_autoneg()
504 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);  in igc_copper_link_autoneg()
509 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);  in igc_copper_link_autoneg()
557 		ret_val = hw->phy.ops.force_speed_duplex(hw);  in igc_setup_copper_link_generic()
574 		hw->mac.ops.config_collision_dist(hw);  in igc_setup_copper_link_generic()
639 	hw->mac.ops.config_collision_dist(hw);  in igc_phy_force_speed_duplex_setup()
666 	if (!hw->phy.ops.read_reg)  in igc_set_d3_lplu_state_generic()
669 	ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data);  in igc_set_d3_lplu_state_generic()
675 		ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,  in igc_set_d3_lplu_state_generic()
685 			ret_val = phy->ops.read_reg(hw,  in igc_set_d3_lplu_state_generic()
692 			ret_val = phy->ops.write_reg(hw,  in igc_set_d3_lplu_state_generic()
698 			ret_val = phy->ops.read_reg(hw,  in igc_set_d3_lplu_state_generic()
705 			ret_val = phy->ops.write_reg(hw,  in igc_set_d3_lplu_state_generic()
715 		ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,  in igc_set_d3_lplu_state_generic()
721 		ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG,  in igc_set_d3_lplu_state_generic()
727 		ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,  in igc_set_d3_lplu_state_generic()
774 	if (!hw->phy.ops.read_reg)  in igc_wait_autoneg()
779 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);  in igc_wait_autoneg()
782 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);  in igc_wait_autoneg()
813 	if (!hw->phy.ops.read_reg)  in igc_phy_has_link_generic()
821 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);  in igc_phy_has_link_generic()
832 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);  in igc_phy_has_link_generic()
865 	if (phy->ops.check_reset_block) {  in igc_phy_hw_reset_generic()
866 		ret_val = phy->ops.check_reset_block(hw);  in igc_phy_hw_reset_generic()
871 	ret_val = phy->ops.acquire(hw);  in igc_phy_hw_reset_generic()
897 	phy->ops.release(hw);  in igc_phy_hw_reset_generic()
915 	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);  in igc_power_up_phy_copper()
917 	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);  in igc_power_up_phy_copper()
934 	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);  in igc_power_down_phy_copper()
936 	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);  in igc_power_down_phy_copper()
958 		ret_val = hw->phy.ops.acquire(hw);  in igc_write_phy_reg_gpy()
964 		hw->phy.ops.release(hw);  in igc_write_phy_reg_gpy()
992 		ret_val = hw->phy.ops.acquire(hw);  in igc_read_phy_reg_gpy()
998 		hw->phy.ops.release(hw);  in igc_read_phy_reg_gpy()
1022 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);  in __igc_access_xmdio_reg()
1026 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);  in __igc_access_xmdio_reg()
1030 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |  in __igc_access_xmdio_reg()
1036 		ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);  in __igc_access_xmdio_reg()
1038 		ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);  in __igc_access_xmdio_reg()
1043 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);  in __igc_access_xmdio_reg()