Lines Matching refs:getOrCreateVReg
290 Register Op0 = getOrCreateVReg(*U.getOperand(0)); in translateBinaryOp()
291 Register Op1 = getOrCreateVReg(*U.getOperand(1)); in translateBinaryOp()
292 Register Res = getOrCreateVReg(U); in translateBinaryOp()
305 Register Op0 = getOrCreateVReg(*U.getOperand(0)); in translateUnaryOp()
306 Register Res = getOrCreateVReg(U); in translateUnaryOp()
323 Register Op0 = getOrCreateVReg(*U.getOperand(0)); in translateCompare()
324 Register Op1 = getOrCreateVReg(*U.getOperand(1)); in translateCompare()
325 Register Res = getOrCreateVReg(U); in translateCompare()
333 Res, getOrCreateVReg(*Constant::getNullValue(U.getType()))); in translateCompare()
336 Res, getOrCreateVReg(*Constant::getAllOnesValue(U.getType()))); in translateCompare()
775 Register SwitchOpReg = getOrCreateVReg(SValue); in emitJumpTableHeader()
796 auto Cst = getOrCreateVReg( in emitJumpTableHeader()
812 Register CondLHS = getOrCreateVReg(*CB.CmpLHS); in emitSwitchCase()
841 Register CondRHS = getOrCreateVReg(*CB.CmpRHS); in emitSwitchCase()
856 Register CmpOpReg = getOrCreateVReg(*CB.CmpMHS); in emitSwitchCase()
858 Register CondRHS = getOrCreateVReg(*CB.CmpRHS); in emitSwitchCase()
1001 Register SwitchOpReg = getOrCreateVReg(*B.SValue); in emitBitTestHeader()
1243 const Register Tgt = getOrCreateVReg(*BrInst.getAddress()); in translateIndirectBr()
1276 Register Base = getOrCreateVReg(*LI.getPointerOperand()); in translateLoad()
1319 Register Base = getOrCreateVReg(*SI.getPointerOperand()); in translateStore()
1414 Register Tst = getOrCreateVReg(*U.getOperand(0)); in translateSelect()
1432 Register Src = getOrCreateVReg(V); in translateCopy()
1457 Register Op = getOrCreateVReg(*U.getOperand(0)); in translateCast()
1458 Register Res = getOrCreateVReg(U); in translateCast()
1466 Register BaseReg = getOrCreateVReg(Op0); in translateGetElementPtr()
1523 Register IdxReg = getOrCreateVReg(*Idx); in translateGetElementPtr()
1552 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0)); in translateGetElementPtr()
1556 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
1572 Register SrcReg = getOrCreateVReg(**AI); in translateMemFunc()
1658 {getOrCreateVReg(*CI.getOperand(0)), getOrCreateVReg(*CI.getOperand(1))}); in translateOverflowIntrinsic()
1665 Register Dst = getOrCreateVReg(CI); in translateFixedPointIntrinsic()
1666 Register Src0 = getOrCreateVReg(*CI.getOperand(0)); in translateFixedPointIntrinsic()
1667 Register Src1 = getOrCreateVReg(*CI.getOperand(1)); in translateFixedPointIntrinsic()
1783 VRegs.push_back(getOrCreateVReg(*Arg)); in translateSimpleIntrinsic()
1785 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs, in translateSimpleIntrinsic()
1825 VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(0))); in translateConstrainedFPIntrinsic()
1827 VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(1))); in translateConstrainedFPIntrinsic()
1829 VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(2))); in translateConstrainedFPIntrinsic()
1831 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(FPI)}, VRegs, Flags); in translateConstrainedFPIntrinsic()
1906 MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address), in translateKnownIntrinsic()
1932 MIRBuilder.buildInstr(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*Ptr)}) in translateKnownIntrinsic()
2016 Register Dst = getOrCreateVReg(CI); in translateKnownIntrinsic()
2017 Register Op0 = getOrCreateVReg(*CI.getArgOperand(0)); in translateKnownIntrinsic()
2018 Register Op1 = getOrCreateVReg(*CI.getArgOperand(1)); in translateKnownIntrinsic()
2019 Register Op2 = getOrCreateVReg(*CI.getArgOperand(2)); in translateKnownIntrinsic()
2038 MIRBuilder.buildFPExt(getOrCreateVReg(CI), in translateKnownIntrinsic()
2039 getOrCreateVReg(*CI.getArgOperand(0)), in translateKnownIntrinsic()
2044 MIRBuilder.buildFPTrunc(getOrCreateVReg(CI), in translateKnownIntrinsic()
2045 getOrCreateVReg(*CI.getArgOperand(0)), in translateKnownIntrinsic()
2058 Register Reg = getOrCreateVReg(CI); in translateKnownIntrinsic()
2070 getStackGuard(getOrCreateVReg(CI), MIRBuilder); in translateKnownIntrinsic()
2082 GuardVal, getOrCreateVReg(*Slot), in translateKnownIntrinsic()
2091 Register Reg = getOrCreateVReg(CI); in translateKnownIntrinsic()
2105 Register Reg = getOrCreateVReg(*CI.getArgOperand(0)); in translateKnownIntrinsic()
2126 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)}, in translateKnownIntrinsic()
2127 {getOrCreateVReg(*CI.getArgOperand(0))}); in translateKnownIntrinsic()
2144 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2145 getOrCreateVReg(*CI.getArgOperand(0))); in translateKnownIntrinsic()
2158 .buildInstr(TargetOpcode::G_READ_REGISTER, {getOrCreateVReg(CI)}, {}) in translateKnownIntrinsic()
2166 .addUse(getOrCreateVReg(*CI.getArgOperand(1))); in translateKnownIntrinsic()
2200 Register Dst = getOrCreateVReg(CI); in translateKnownIntrinsic()
2201 Register ScalarSrc = getOrCreateVReg(*CI.getArgOperand(0)); in translateKnownIntrinsic()
2202 Register VecSrc = getOrCreateVReg(*CI.getArgOperand(1)); in translateKnownIntrinsic()
2294 [&]() { return getOrCreateVReg(*CB.getCalledOperand()); }); in translateCallBase()
2614 Register Res = getOrCreateVReg(AI); in translateAlloca()
2625 Register NumElts = getOrCreateVReg(*AI.getArraySize()); in translateAlloca()
2638 getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, DL->getTypeAllocSize(Ty))); in translateAlloca()
2655 MIRBuilder.buildDynStackAlloc(getOrCreateVReg(AI), AlignedAlloc, Alignment); in translateAlloca()
2667 MIRBuilder.buildInstr(TargetOpcode::G_VAARG, {getOrCreateVReg(U)}, in translateVAArg()
2668 {getOrCreateVReg(*U.getOperand(0)), in translateVAArg()
2680 Register Res = getOrCreateVReg(U); in translateInsertElement()
2681 Register Val = getOrCreateVReg(*U.getOperand(0)); in translateInsertElement()
2682 Register Elt = getOrCreateVReg(*U.getOperand(1)); in translateInsertElement()
2683 Register Idx = getOrCreateVReg(*U.getOperand(2)); in translateInsertElement()
2695 Register Res = getOrCreateVReg(U); in translateExtractElement()
2696 Register Val = getOrCreateVReg(*U.getOperand(0)); in translateExtractElement()
2704 Idx = getOrCreateVReg(*NewIdxCI); in translateExtractElement()
2708 Idx = getOrCreateVReg(*U.getOperand(1)); in translateExtractElement()
2726 .buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {getOrCreateVReg(U)}, in translateShuffleVector()
2727 {getOrCreateVReg(*U.getOperand(0)), in translateShuffleVector()
2728 getOrCreateVReg(*U.getOperand(1))}) in translateShuffleVector()
2756 Register Addr = getOrCreateVReg(*I.getPointerOperand()); in translateAtomicCmpXchg()
2757 Register Cmp = getOrCreateVReg(*I.getCompareOperand()); in translateAtomicCmpXchg()
2758 Register NewVal = getOrCreateVReg(*I.getNewValOperand()); in translateAtomicCmpXchg()
2778 Register Res = getOrCreateVReg(I); in translateAtomicRMW()
2779 Register Addr = getOrCreateVReg(*I.getPointerOperand()); in translateAtomicRMW()
2780 Register Val = getOrCreateVReg(*I.getValOperand()); in translateAtomicRMW()
2949 Ops.push_back(getOrCreateVReg(Elt)); in translate()
2960 Ops.push_back(getOrCreateVReg(Elt)); in translate()
2977 Ops.push_back(getOrCreateVReg(*CV->getOperand(i))); in translate()