Lines Matching refs:Cases
531 const std::vector<SwitchCG::CaseBlock> &Cases) { in shouldEmitAsBranches() argument
533 if (Cases.size() != 2) in shouldEmitAsBranches()
538 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && in shouldEmitAsBranches()
539 Cases[0].CmpRHS == Cases[1].CmpRHS) || in shouldEmitAsBranches()
540 (Cases[0].CmpRHS == Cases[1].CmpLHS && in shouldEmitAsBranches()
541 Cases[0].CmpLHS == Cases[1].CmpRHS)) { in shouldEmitAsBranches()
547 if (Cases[0].CmpRHS == Cases[1].CmpRHS && in shouldEmitAsBranches()
548 Cases[0].PredInfo.Pred == Cases[1].PredInfo.Pred && in shouldEmitAsBranches()
549 isa<Constant>(Cases[0].CmpRHS) && in shouldEmitAsBranches()
550 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { in shouldEmitAsBranches()
551 if (Cases[0].PredInfo.Pred == CmpInst::ICMP_EQ && in shouldEmitAsBranches()
552 Cases[0].TrueBB == Cases[1].ThisBB) in shouldEmitAsBranches()
554 if (Cases[0].PredInfo.Pred == CmpInst::ICMP_NE && in shouldEmitAsBranches()
555 Cases[0].FalseBB == Cases[1].ThisBB) in shouldEmitAsBranches()
1009 for (unsigned I = 0, E = B.Cases.size(); I != E; ++I) { in emitBitTestHeader()
1010 if (!isUIntN(SwitchOpTy.getSizeInBits(), B.Cases[I].Mask)) { in emitBitTestHeader()
1024 MachineBasicBlock *MBB = B.Cases[0].ThisBB; in emitBitTestHeader()
1116 for (BitTestCase &BTC : BTB->Cases) in lowerBitTestWorkItem()
2995 for (unsigned j = 0, ej = BTB.Cases.size(); j != ej; ++j) { in finalizeBasicBlock()
2996 UnhandledProb -= BTB.Cases[j].ExtraProb; in finalizeBasicBlock()
2998 MachineBasicBlock *MBB = BTB.Cases[j].ThisBB; in finalizeBasicBlock()
3011 NextMBB = BTB.Cases[j + 1].TargetBB; in finalizeBasicBlock()
3017 NextMBB = BTB.Cases[j + 1].ThisBB; in finalizeBasicBlock()
3020 emitBitTestCase(BTB, NextMBB, UnhandledProb, BTB.Reg, BTB.Cases[j], MBB); in finalizeBasicBlock()
3027 BTB.Cases[ej - 1].TargetBB->getBasicBlock()}, in finalizeBasicBlock()
3030 BTB.Cases.pop_back(); in finalizeBasicBlock()
3040 addMachineCFGPred(HeaderToDefaultEdge, BTB.Cases.back().ThisBB); in finalizeBasicBlock()