397     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);  in materializeFP()  local
398     emitInst(Mips::MTC1, DestReg).addReg(TempReg);  in materializeFP()
428     unsigned TempReg = createResultReg(RC);  in materializeGV()  local
429     emitInst(Mips::ADDiu, TempReg)  in materializeGV()
432     DestReg = TempReg;  in materializeGV()
654     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()  local
655     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);  in emitCmp()
656     emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
660     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()  local
661     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);  in emitCmp()
662     emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);  in emitCmp()
672     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()  local
673     emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);  in emitCmp()
674     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
678     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()  local
679     emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);  in emitCmp()
680     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
690     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()  local
691     emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);  in emitCmp()
692     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
696     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()  local
697     emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);  in emitCmp()
698     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
1063   unsigned TempReg = createResultReg(RC);  in selectSelect()  local
1065   if (!ResultReg || !TempReg)  in selectSelect()
1068   emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);  in selectSelect()
1070     .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);  in selectSelect()
1129   unsigned TempReg = createResultReg(&Mips::FGR32RegClass);  in selectFPToInt()  local
1133   emitInst(Opc, TempReg).addReg(SrcReg);  in selectFPToInt()
1134   emitInst(Mips::MFC1, DestReg).addReg(TempReg);  in selectFPToInt()
1607         unsigned TempReg[3];  in fastLowerIntrinsicCall()  local
1609           TempReg[i] = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1610           if (TempReg[i] == 0)  in fastLowerIntrinsicCall()
1613         emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);  in fastLowerIntrinsicCall()
1614         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);  in fastLowerIntrinsicCall()
1615         emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);  in fastLowerIntrinsicCall()
1616         emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);  in fastLowerIntrinsicCall()
1622         unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()  local
1623         emitInst(Mips::WSBH, TempReg).addReg(SrcReg);  in fastLowerIntrinsicCall()
1624         emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);  in fastLowerIntrinsicCall()
1628         unsigned TempReg[8];  in fastLowerIntrinsicCall()  local
1630           TempReg[i] = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1631           if (TempReg[i] == 0)  in fastLowerIntrinsicCall()
1635         emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);  in fastLowerIntrinsicCall()
1636         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);  in fastLowerIntrinsicCall()
1637         emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);  in fastLowerIntrinsicCall()
1638         emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);  in fastLowerIntrinsicCall()
1640         emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);  in fastLowerIntrinsicCall()
1641         emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);  in fastLowerIntrinsicCall()
1643         emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);  in fastLowerIntrinsicCall()
1644         emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);  in fastLowerIntrinsicCall()
1645         emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);  in fastLowerIntrinsicCall()
1840   unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitIntSExt32r1()  local
1841   emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);  in emitIntSExt32r1()
1842   emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);  in emitIntSExt32r1()
1975     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in selectShift()  local
1976     if (!TempReg)  in selectShift()
1981     if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))  in selectShift()
1984     Op0Reg = TempReg;  in selectShift()
2101     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in getRegEnsuringSimpleIntegerWidening()  local
2102     if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))  in getRegEnsuringSimpleIntegerWidening()
2104     VReg = TempReg;  in getRegEnsuringSimpleIntegerWidening()
2111     unsigned TempReg =  in simplifyAddress()  local
2114     emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());  in simplifyAddress()