Lines Matching refs:SrcVT
188 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
189 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
192 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
195 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
197 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1001 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPExt() local
1004 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1080 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPTrunc() local
1083 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
1103 MVT DstVT, SrcVT; in selectFPToInt() local
1116 if (!isTypeLegal(SrcTy, SrcVT)) in selectFPToInt()
1119 if (SrcVT != MVT::f32 && SrcVT != MVT::f64) in selectFPToInt()
1130 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32; in selectFPToInt()
1208 MVT SrcVT = ArgVT; in processCallArgs() local
1209 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
1216 MVT SrcVT = ArgVT; in processCallArgs() local
1217 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
1780 EVT SrcVT, DestVT; in selectTrunc() local
1781 SrcVT = TLI.getValueType(DL, Op->getType(), true); in selectTrunc()
1784 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in selectTrunc()
1817 MVT SrcVT = SrcEVT.getSimpleVT(); in selectIntExt() local
1821 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt)) in selectIntExt()
1827 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntSExt32r1() argument
1830 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1846 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntSExt32r2() argument
1848 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1861 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntSExt() argument
1866 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg); in emitIntSExt()
1867 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg); in emitIntSExt()
1870 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntZExt() argument
1874 switch (SrcVT.SimpleTy) { in emitIntZExt()
1892 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() argument
1899 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16))) in emitIntExt()
1902 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg); in emitIntExt()
1903 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg); in emitIntExt()
1906 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() argument
1909 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt); in emitIntExt()