Lines Matching refs:LeftReg
642 unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned); in emitCmp() local
643 if (LeftReg == 0) in emitCmp()
655 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
661 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
666 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
669 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
673 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
679 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
684 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
687 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
691 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
697 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
746 emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg) in emitCmp()