139   SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
141                         unsigned NumOps, bool isSigned, const SDLoc &dl);
144                                                  SDNode *Node, bool isSigned);
149   SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
170   SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, EVT DestVT,
172   SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
174   SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
1995                                             bool isSigned) {  in ExpandLibCall()  argument
2003     Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);  in ExpandLibCall()
2004     Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);  in ExpandLibCall()
2030   bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);  in ExpandLibCall()
2056                                             bool isSigned, const SDLoc &dl) {  in ExpandLibCall()  argument
2064     Entry.IsSExt = isSigned;  in ExpandLibCall()
2065     Entry.IsZExt = !isSigned;  in ExpandLibCall()
2078       .setSExtResult(isSigned)  in ExpandLibCall()
2079       .setZExtResult(!isSigned)  in ExpandLibCall()
2092                                          bool isSigned) {  in ExpandChainLibCall()  argument
2102     Entry.IsSExt = isSigned;  in ExpandChainLibCall()
2103     Entry.IsZExt = !isSigned;  in ExpandChainLibCall()
2116       .setSExtResult(isSigned)  in ExpandChainLibCall()
2117       .setZExtResult(!isSigned);  in ExpandChainLibCall()
2145 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,  in ExpandIntLibCall()  argument
2160   return ExpandLibCall(LC, Node, isSigned);  in ExpandIntLibCall()
2168   bool isSigned = Opcode == ISD::SDIVREM;  in ExpandDivRemLibCall()  local
2173   case MVT::i8:   LC= isSigned ? RTLIB::SDIVREM_I8  : RTLIB::UDIVREM_I8;  break;  in ExpandDivRemLibCall()
2174   case MVT::i16:  LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;  in ExpandDivRemLibCall()
2175   case MVT::i32:  LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;  in ExpandDivRemLibCall()
2176   case MVT::i64:  LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;  in ExpandDivRemLibCall()
2177   case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;  in ExpandDivRemLibCall()
2195     Entry.IsSExt = isSigned;  in ExpandDivRemLibCall()
2196     Entry.IsZExt = !isSigned;  in ExpandDivRemLibCall()
2204   Entry.IsSExt = isSigned;  in ExpandDivRemLibCall()
2205   Entry.IsZExt = !isSigned;  in ExpandDivRemLibCall()
2217       .setSExtResult(isSigned)  in ExpandDivRemLibCall()
2218       .setZExtResult(!isSigned);  in ExpandDivRemLibCall()
2330 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0,  in ExpandLegalINT_TO_FP()  argument
2356     if (isSigned) {  in ExpandLegalINT_TO_FP()
2375     SDValue Bias = DAG.getConstantFP(isSigned ?  in ExpandLegalINT_TO_FP()
2385   assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");  in ExpandLegalINT_TO_FP()
2443                                                     bool isSigned,  in PromoteLegalINT_TO_FP()  argument
2460     if (isSigned) continue;  in PromoteLegalINT_TO_FP()
2474                      DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,  in PromoteLegalINT_TO_FP()
2484                                                     bool isSigned,  in PromoteLegalFP_TO_INT()  argument
2504     if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {  in PromoteLegalFP_TO_INT()
3155     bool isSigned = Node->getOpcode() == ISD::SREM;  in ExpandNode()  local
3156     unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;  in ExpandNode()
3157     unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;  in ExpandNode()
3175     bool isSigned = Node->getOpcode() == ISD::SDIV;  in ExpandNode()  local
3176     unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;  in ExpandNode()
3369     bool isSigned = Node->getOpcode() == ISD::SMULO;  in ExpandNode()  local
3370     if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {  in ExpandNode()
3372       TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);  in ExpandNode()
3373     } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {  in ExpandNode()
3374       BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,  in ExpandNode()
3378       LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);  in ExpandNode()
3379       RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);  in ExpandNode()
3403       if (isSigned) {  in ExpandNode()
3431         Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);  in ExpandNode()
3434         Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);  in ExpandNode()
3442     if (isSigned) {  in ExpandNode()