1201 	ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);  in ice_pf_enable_irq0()
1205 	ICE_WRITE_REG(hw, PFINT_OICR_ENA,  in ice_pf_enable_irq0()
1209 	ICE_WRITE_REG(hw, PFINT_OICR_CTL,  in ice_pf_enable_irq0()
1215 	ICE_WRITE_REG(hw, PFINT_FW_CTL,  in ice_pf_enable_irq0()
1221 	ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);  in ice_pf_enable_irq0()
1224 	ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),  in ice_pf_enable_irq0()
1237 	ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);  in ice_pf_disable_irq0()
2412 		ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);  in ice_vsi_disable_queues_intr()
2413 		ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);  in ice_vsi_disable_queues_intr()
2421 			ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),  in ice_vsi_disable_queues_intr()
2426 		ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);  in ice_vsi_disable_queues_intr()
2512 		ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(pin_idx, timer), 0);  in ice_dev_close()
2513 		ICE_WRITE_REG(hw, GLTSYN_CLKO(pin_idx, timer), 0);  in ice_dev_close()
2514 		ICE_WRITE_REG(hw, GLTSYN_TGT_L(pin_idx, timer), 0);  in ice_dev_close()
2515 		ICE_WRITE_REG(hw, GLTSYN_TGT_H(pin_idx, timer), 0);  in ice_dev_close()
2518 		ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(pin_idx), val);  in ice_dev_close()
3288 	ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);  in ice_init_rss()
3355 			ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1);  in __vsi_queues_bind_intr()
3356 			ICE_WRITE_REG(hw, QRX_ITR(base_queue + i),  in __vsi_queues_bind_intr()
3359 			ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);  in __vsi_queues_bind_intr()
3360 			ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), 0);  in __vsi_queues_bind_intr()
3363 		ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);  in __vsi_queues_bind_intr()
3364 		ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);  in __vsi_queues_bind_intr()
3384 		ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);  in ice_vsi_queues_bind_intr()
3385 		ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);  in ice_vsi_queues_bind_intr()
3437 			ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),  in ice_vsi_enable_queues_intr()
3444 		ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),  in ice_vsi_enable_queues_intr()
3546 	ICE_WRITE_REG(hw, GLTSYN_CLKO(idx, timer), NSEC_PER_SEC / 2);  in ice_pps_out_cfg()
3549 	ICE_WRITE_REG(hw, GLTSYN_TGT_L(idx, timer), start_time & 0xffffffff);  in ice_pps_out_cfg()
3550 	ICE_WRITE_REG(hw, GLTSYN_TGT_H(idx, timer), start_time >> 32);  in ice_pps_out_cfg()
3553 	ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(idx, timer),  in ice_pps_out_cfg()
3557 	ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(idx), val);  in ice_pps_out_cfg()
4487 			ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);  in ice_set_rss_lut()
4796 	ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);  in ice_rx_queue_intr_enable()
4812 	ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);  in ice_rx_queue_intr_disable()
5859 	ICE_WRITE_REG(hw, GLTSYN_ENA(0), val);  in ice_timesync_disable()
5861 	ICE_WRITE_REG(hw, GLTSYN_INCVAL_L(0), 0);  in ice_timesync_disable()
5862 	ICE_WRITE_REG(hw, GLTSYN_INCVAL_H(0), 0);  in ice_timesync_disable()