| 4f8a96ad | 09-Aug-2024 |
Afonso Bordado <[email protected]> |
riscv64: Refactor Floating Point Instruction Emission (#9084)
* riscv64: Refactor FpuRR instruction emission
Previously we had opcodes for each instruction length variant, with the width field impl
riscv64: Refactor Floating Point Instruction Emission (#9084)
* riscv64: Refactor FpuRR instruction emission
Previously we had opcodes for each instruction length variant, with the width field implicitly embedded in the `funct7` field of the opcode.
This works, but the instructions are defined with the width field having a few more possible values. In order to add FP16 support to these instructions we would have to duplicate the opcodes.
Instead make these opcodes width agnostic and specifiy the width during emission.
* riscv64: Refactor FpuRRR instruction emission
Previously we had opcodes for each instruction length variant, with the width field implicitly embedded in the `funct7` field of the opcode.
This works, but the instructions are defined with the width field having a few more possible values. In order to add FP16 support to these instructions we would have to duplicate the opcodes.
Instead make these opcodes width agnostic and specifiy the width during emission.
* riscv64: Refactor FpuRRRR instruction emission
Previously we had opcodes for each instruction length variant, with the width field implicitly embedded in the `funct7` field of the opcode.
This works, but the instructions are defined with the width field having a few more possible values. In order to add FP16 support to these instructions we would have to duplicate the opcodes.
Instead make these opcodes width agnostic and specifiy the width during emission.
* riscv64: Fix emit tests
* riscv64: Run `cargo fmt`
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