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Revision tags: dev, v36.0.9, v44.0.1, v43.0.2, v36.0.8, v24.0.8, v44.0.0, v43.0.1, v42.0.2, v36.0.7, v24.0.7, v43.0.0, v42.0.1, v41.0.4, v42.0.0, v40.0.4, v36.0.6, v24.0.6, v41.0.3, v41.0.2, v41.0.1, v36.0.5, v40.0.3, v41.0.0, v36.0.4, v39.0.2, v40.0.2, v40.0.1, v40.0.0, v39.0.1, v39.0.0, v38.0.4, v37.0.3, v36.0.3, v24.0.5, v38.0.3, v38.0.2, v38.0.1, v37.0.2 |
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| #
2a2e8f62 |
| 01-Oct-2025 |
bjorn3 <[email protected]> |
Couple cleanups to the flags/settings handling in Cranelift (#11744)
* Remove unused shared flags
* Get rid of predicate settings
They were important in the old backend framework, but with the new
Couple cleanups to the flags/settings handling in Cranelift (#11744)
* Remove unused shared flags
* Get rid of predicate settings
They were important in the old backend framework, but with the new
backend framework if we need a combination of multiple settings, that
can just be done as a regular extractor doing &&. This simplifies the
settings implementation.
show more ...
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Revision tags: v37.0.1, v37.0.0, v36.0.2, v36.0.1, v36.0.0, v35.0.0, v24.0.4, v33.0.2, v34.0.2, v34.0.1, v33.0.1, v24.0.3, v32.0.1, v34.0.0, v33.0.0, v32.0.0, v31.0.0, v30.0.2, v30.0.1, v30.0.0, v29.0.1, v29.0.0, v28.0.1, v28.0.0, v27.0.0, v26.0.1, v25.0.3, v24.0.2, v26.0.0, v21.0.2, v22.0.1, v23.0.3, v25.0.2, v24.0.1, v25.0.1, v25.0.0, v24.0.0, v23.0.2, v23.0.1, v23.0.0, v22.0.0, v21.0.1, v21.0.0, v20.0.2, v20.0.1, v20.0.0, v17.0.3, v19.0.2, v18.0.4, v19.0.1, v19.0.0, v18.0.3, v18.0.2, v17.0.2, v18.0.1, v18.0.0, v17.0.1, v17.0.0, v16.0.0, v15.0.1, v15.0.0, v14.0.4, v14.0.3, v14.0.2, v13.0.1, v14.0.1, v14.0.0, minimum-viable-wasi-proxy-serve, v13.0.0, v12.0.2, v11.0.2, v10.0.2, v12.0.1, v12.0.0, v11.0.1, v11.0.0, v10.0.1, v10.0.0, v9.0.4, v9.0.3, v9.0.2, v9.0.1, v9.0.0, v6.0.2, v7.0.1, v8.0.1 |
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| #
4337ccd4 |
| 25-Apr-2023 |
Afonso Bordado <[email protected]> |
riscv64: Support non 128bit vector sizes (#6266)
* riscv64: Add `Zvl` extensions
* riscv64: Allow lowering SIMD operations that fit in a vector register
* riscv64: Support non 128bit vector sizes
riscv64: Support non 128bit vector sizes (#6266)
* riscv64: Add `Zvl` extensions
* riscv64: Allow lowering SIMD operations that fit in a vector register
* riscv64: Support non 128bit vector sizes
* riscv64: Add Zvl Presets
* riscv64: Precompute `min_vec_reg_size`
show more ...
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Revision tags: v8.0.0, v7.0.0, v6.0.1, v5.0.1, v4.0.1, v6.0.0, v5.0.0 |
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8ac04612 |
| 09-Jan-2023 |
Afonso Bordado <[email protected]> |
cranelift: Remove predicate not macro branch (#5552)
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Revision tags: v4.0.0, v3.0.1, v3.0.0, v1.0.2, v2.0.2, v2.0.1, v2.0.0, v1.0.1, v1.0.0, v0.40.1, v0.40.0, v0.39.1, v0.38.3, v0.38.2, v0.39.0, v0.38.1, v0.38.0, v0.37.0, v0.36.0, v0.35.3, v0.34.2, v0.35.2, v0.35.1, v0.35.0, v0.33.1, v0.34.1, v0.34.0, v0.33.0, v0.32.1, v0.32.0, v0.31.0 |
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| #
6b32fcfc |
| 12-Oct-2021 |
bjorn3 <[email protected]> |
Remove Constraint
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Revision tags: v0.30.0, v0.29.0 |
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| #
3e4167ba |
| 21-Jun-2021 |
bjorn3 <[email protected]> |
Remove registers from cranelift-codegen-meta
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| #
18bd27e9 |
| 21-Jun-2021 |
bjorn3 <[email protected]> |
Remove legalizer support from cranelift-codegen-meta
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d4999336 |
| 21-Jun-2021 |
bjorn3 <[email protected]> |
Remove encoding generation from cranelift-codegen-meta
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Revision tags: v0.28.0, v0.26.1, v0.27.0, v0.26.0, v0.25.0, v0.24.0, v0.23.0, v0.22.1, cranelift-v0.69.0, v0.22.0, v0.21.0, v0.20.0, v0.19.0, v0.18.0, v0.17.0, v0.16.0, v0.15.0, cranelift-v0.62.0, cranelift-v0.61.0, cranelift-v0.60.0, v0.12.0, v0.11.0, v0.10.0, v0.9.0, v0.8.0, v0.6.0, v0.4.0 |
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| #
f1945664 |
| 31-Oct-2019 |
Andrew Brown <[email protected]> |
Add documentation for top-level items in cranelift-codegen/meta
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Revision tags: cranelift-v0.46.1, cranelift-v0.46.0, cranelift-v0.45.0, cranelift-v0.44.0, cranelift-v0.43.1, cranelift-v0.43.0, cranelift-v0.42.0, cranelift-v0.41.0, v0.3.0, v0.2.0, cranelift-v0.40.0, cranelift-v0.39.0, cranelift-v0.37.0, cranelift-v0.36.0, cranelift-v0.35.0, cranelift-v0.34.0, cranelift-v0.33.0, cranelift-v0.32.0, cranelift-v0.31.0 |
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| #
21aaf0c8 |
| 24-Jun-2019 |
Benjamin Bouvier <[email protected]> |
[meta] Add cdsl facilities for encodings and recipes;
Co-authored-by: Benjamin Bouvier <[email protected]>
Co-authored-by: bjorn3 <[email protected]>
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22a68234 |
| 30-Apr-2019 |
Benjamin Bouvier <[email protected]> |
[meta] Rename cdsl/inst to cdsl/instructions;
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390cfb37 |
| 16-Apr-2019 |
Benjamin Bouvier <[email protected]> |
[meta] Use named predicates for x86 settings in the Rust crate too;
And generate them using the same deterministic order that the Python
code uses.
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1f21349c |
| 18-Apr-2019 |
Benjamin Bouvier <[email protected]> |
[meta] Add CPU modes to the meta crate;
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494f3abf |
| 18-Apr-2019 |
Benjamin Bouvier <[email protected]> |
[meta] Add type inference, transforms and AST helpers for legalization;
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3c31eac4 |
| 11-Mar-2019 |
Benjamin Bouvier <[email protected]> |
[meta] Port Instruction/InstructionGroup to the Rust meta crate;
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d59bef19 |
| 11-Mar-2019 |
Benjamin Bouvier <[email protected]> |
[meta] Port Formats and Operands to the Rust crate;
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146e0bd2 |
| 11-Mar-2019 |
Benjamin Bouvier <[email protected]> |
[meta] Port Typevar to the Rust crate;
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747ad3c4 |
| 28-Jan-2019 |
lazypassion <[email protected]> |
moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
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