lspci: Decode all defined fields in the Device Capabilities 2 register

Decode all defined fields in the Device Capabilities 2 register.

The difference from "lspci -vv" output now looks like this:

lspci: Decode all defined fields in the Device Capabilities 2 register

Decode all defined fields in the Device Capabilities 2 register.

The difference from "lspci -vv" output now looks like this:

- DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
+ DevCap2: Completion Timeout: Range ABC, TimeoutDis+, NROPrPrP-, LTR+
+ 10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt-, EETLPPrefix-
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS-, LN System CLS Not Supported, TPHComp-, ExtTPHComp-, ARIFwd+

Signed-off-by: Frederick Lawler <[email protected]>

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lspci: Indent PCIe Capability DevCap2 & DevCtl2 correctly

Indent the AtomicOpsCap and AtomicOpsCtl fields to make it clear that these
are part of the DevCap2 and DevCtl2 registers.

The difference i

lspci: Indent PCIe Capability DevCap2 & DevCtl2 correctly

Indent the AtomicOpsCap and AtomicOpsCtl fields to make it clear that these
are part of the DevCap2 and DevCtl2 registers.

The difference in the "lspci -vv" output looks like this:

DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
- AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
+ AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd-
- AtomicOpsCtl: ReqEn- EgressBlck-
+ AtomicOpsCtl: ReqEn- EgressBlck-

Signed-off-by: Bjorn Helgaas <[email protected]>

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