Flit Mode and Device 3 Capability

lspci: Add test case for Physical Layer 16 GT/s and 32 GT/s extended capability registers

lspci: add VirtIO SharedMemory capability support

This patch adds the support for VirtIO share memory capability [1].
A shared memory region is defined in a `struct virtio_pci_cap64`
where the highe

lspci: add VirtIO SharedMemory capability support

This patch adds the support for VirtIO share memory capability [1].
A shared memory region is defined in a `struct virtio_pci_cap64`
where the highest 32 bits of `offset` and `size` are appened to the
original `struct virtio_pci_cap`.

With this patch, a VirtIO PMEM device (ID 27) shows like the
following:

```
00:02.0 Class ffff: Device 1af4:105b (rev 01)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Region 0: Memory at 100001000 (64-bit, non-prefetchable) [size=4K]
Region 2: Memory at 101000000 (64-bit, non-prefetchable) [size=16M]
Capabilities: [40] Vendor Specific Information: VirtIO: CommonCfg
BAR=0 offset=00000000 size=0000003c
Capabilities: [50] Vendor Specific Information: VirtIO: ISR
BAR=0 offset=0000003c size=00000001
Capabilities: [60] Vendor Specific Information: VirtIO: Notify
BAR=0 offset=00000040 size=00000002 multiplier=00000002
Capabilities: [78] MSI-X: Enable+ Count=2 Masked-
Vector table: BAR=0 offset=00000058
PBA: BAR=0 offset=00000078
Capabilities: [88] Vendor Specific Information: VirtIO: DeviceCfg
BAR=0 offset=00000044 size=00000010
Capabilities: [98] Vendor Specific Information: VirtIO: SharedMemory
BAR=2 offset=0000000000000000 size=0000000001000000 id=0
Kernel driver in use: virtio-pci
```

[1] Sec 4.1.4.7 https://docs.oasis-open.org/virtio/virtio/v1.2/csd01/virtio-v1.2-csd01.html#x1-1240004

Signed-off-by: Changyuan Lyu <[email protected]>

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ls-ecaps: Correct the link state reporting

PCIe r6.0, sec 7.9.26.4.2 "Link IDE Stream Status Register defines"
the link state as:

0000b Insecure
0010b Secure

The same definition applies to selecti

ls-ecaps: Correct the link state reporting

PCIe r6.0, sec 7.9.26.4.2 "Link IDE Stream Status Register defines"
the link state as:

0000b Insecure
0010b Secure

The same definition applies to selective streams as well.
The existing code wrongly assumes "secure" is 0001b, fix that for both
link and selective streams.

While at this, add missing "Selective IDE for Configuration Requests Enable".
Also fix the base and limit parsing for the memory and RID ranges.

Fixes: 42fc4263ec0e ("ls-ecaps: Add decode support for IDE Extended Capability")
Signed-off-by: Alexey Kardashevskiy <[email protected]>

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ls-ecaps: Add decode support for IDE Extended Capability

IDE (Integrity & Data Encryption) Extended Capability defined in [1]
implements control of the PCI link encryption. The verbose level > 2 pri

ls-ecaps: Add decode support for IDE Extended Capability

IDE (Integrity & Data Encryption) Extended Capability defined in [1]
implements control of the PCI link encryption. The verbose level > 2 prints
offsets of the fields to make running setpci easier.

The example output is:

Capabilities: [830 v1] Integrity & Data Encryption
IDECap: Lnk=0 Sel=1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM+ Alg='AES-GCM-256-96b' TCs=8 TeeLim+
IDECtl: FTEn-
SelectiveIDE#0 Cap: RID#=1
SelectiveIDE#0 Ctl: En- NPR- PR- CPL- PCRC- HdrEnc=no Alg='AES-GCM-256-96b' TC0 ID0
SelectiveIDE#0 Sta: insecure RecvChkFail-
SelectiveIDE#0 RID: Valid- Base=0 Limit=0 SegBase=0
SelectiveIDE#0 RID#0: Valid- Base=0 Limit=0

[1] PCIe r6.0.1, sections 6.33, 7.9.26

Signed-off-by: Alexey Kardashevskiy <[email protected]>

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Subject: lspci: Display PASID required attribute in Page Status Register.

Display the PASID required attribute in the Page Request Status Register.
When set, the function expects a PASID on Page Gro

Subject: lspci: Display PASID required attribute in Page Status Register.

Display the PASID required attribute in the Page Request Status Register.
When set, the function expects a PASID on Page Group Response (PRG)
messages when the corresponding page request had a PASID.

Signed-off-by: Ashok Raj <[email protected]>

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Add test case with multidomain Freescale P2020 PCIe hierarchy

lspci: Add test case for CXL device

Add requested config space dump of CXL device for testing

Signed-off-by: Jaxon Haws <[email protected]>

pciutils: Add decode support for Data Object Exchange Extended Capability

PCI Data Object Exchange [1] provides a mailbox interface used as the
transport for various protocols defined by PCI-SIG and

pciutils: Add decode support for Data Object Exchange Extended Capability

PCI Data Object Exchange [1] provides a mailbox interface used as the
transport for various protocols defined by PCI-SIG and others. Make the
limited information in config space available. Note the Read/Write
Mailbox registers themselves are not currently parsed as the usefulness
of accessing one dword of a protocol is probably limited.

In future, operating systems may provide means to safely query the
supported protocols, but those have not yet been defined.

Example output:

Capabilities: [100 v1] Data Object Exchange
DOECap: IntSup+
Interrupt Message Number 001
DOECtl: IntEn+
DOESta: Busy- IntSta- Error- ObjectReady+

[1] PCIe r6.0, sections 6.30 and 7.9.24

Signed-off-by: Jonathan Cameron <[email protected]>

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lspci: Update tests files with VF 10-Bit Tag Requester

Update the tests files with the new field 10BitTagReq
in SR-IOV Capabilities Register.

Signed-off-by: Dongdong Liu <[email protected]>

pciutils: Add decode support for RCECs

Root Complex Event Collectors provide support for terminating error
and PME messages from RCiEPs. This patch provides basic decoding for
the lspci RCEC Endpoi

pciutils: Add decode support for RCECs

Root Complex Event Collectors provide support for terminating error
and PME messages from RCiEPs. This patch provides basic decoding for
the lspci RCEC Endpoint Association Extended Capability. See PCIe 5.0-1,
sec 7.9.10 for further details.

Suggested-by: Bjorn Helgaas <[email protected]>
Signed-off-by: Sean V Kelley <[email protected]>

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CXL: Capability vendor ID changed

Update the cap-dvsec-cxl test to match the new vendor ID.

Signed-off-by: Sean V Kelley <[email protected]>

lspci: Decode the (virtual) resizeble BAR capability

A patch by Paul Blinzer.

Tests: cap-dvsec was superseded by cap-dvsec-cxl

Tests: cap-dvsec-cxl had tabs erroneously expanded to spaces

pciutils: Decode Compute eXpress Link DVSEC

Compute eXpress Link[1] is a new CPU interconnect created with
workload accelerators in mind. The interconnect relies on PCIe
electrical and physical inte

pciutils: Decode Compute eXpress Link DVSEC

Compute eXpress Link[1] is a new CPU interconnect created with
workload accelerators in mind. The interconnect relies on PCIe
electrical and physical interconnect for communication via a Flex Bus
port which allows designs to choose between providing PCIe or CXL.

This patch introduces basic support for lspci decode of CXL and
builds upon the existing Designated Vendor-Specific support in
lspci through identification of a supporting CXL device using DVSEC
Vendor ID and DVSEC ID.

[1] https://www.computeexpresslink.org/

Signed-off-by: Sean V Kelley <[email protected]>

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pciutils: Decode available DVSEC details

Instead of current generic 'unknown' output for DVSEC, decode details on
Vendor ID, Rev, etc.

Suggested-by: Bjorn Helgaas <[email protected]>
Signed-off-b

pciutils: Decode available DVSEC details

Instead of current generic 'unknown' output for DVSEC, decode details on
Vendor ID, Rev, etc.

Suggested-by: Bjorn Helgaas <[email protected]>
Signed-off-by: Sean V Kelley <[email protected]>

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lspci: Decode PCIe Link Capabilities 2, expand Link Status 2

Decode Link Capabilities 2, which includes the Supported Link Speeds
Vector, and decode more fields of Link Status 2.

The test case (dat

lspci: Decode PCIe Link Capabilities 2, expand Link Status 2

Decode Link Capabilities 2, which includes the Supported Link Speeds
Vector, and decode more fields of Link Status 2.

The test case (data from https://bugzilla.kernel.org/show_bug.cgi?id=206837
comment #21) includes a Thunderbolt Downstream Port that advertises
2.5-8GT/s support in Link Capabilities 2.

Signed-off-by: Bjorn Helgaas <[email protected]>

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lspci: Decode all defined fields in the Device Capabilities 2 register

Decode all defined fields in the Device Capabilities 2 register.

The difference from "lspci -vv" output now looks like this:

lspci: Decode all defined fields in the Device Capabilities 2 register

Decode all defined fields in the Device Capabilities 2 register.

The difference from "lspci -vv" output now looks like this:

- DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
+ DevCap2: Completion Timeout: Range ABC, TimeoutDis+, NROPrPrP-, LTR+
+ 10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt-, EETLPPrefix-
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS-, LN System CLS Not Supported, TPHComp-, ExtTPHComp-, ARIFwd+

Signed-off-by: Frederick Lawler <[email protected]>

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lspci: Decode Multicast Extended Capability

Decode the Multicast Extended Capability described in PCIe r4.0, sec
7.9.11.

Signed-off-by: Bjorn Helgaas <[email protected]>

Added test cases for topology computation

Contributed by Matthew Wilcox

lspci: Avoid "%1$c" style format strings in HT capability

This kind of format strings is not available on some compilers.

Also added a test case for the HT capability.

lspci: Decode "VGA 16-bit decode" in bridge control register

Decode the "VGA 16-bit decode" bit in the bridge control register. This
bit was added in the PCI-to-PCI Bridge Arch Spec, r1.2, sec 3.2.

lspci: Decode "VGA 16-bit decode" in bridge control register

Decode the "VGA 16-bit decode" bit in the bridge control register. This
bit was added in the PCI-to-PCI Bridge Arch Spec, r1.2, sec 3.2.5.18.
Note that the bit is only meaningful if the VGA Enable bit or the VGA
Palette Snoop Enable bit is set.

Signed-off-by: Bjorn Helgaas <[email protected]>

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lspci: Decode only supported ASPM exit latencies

Per PCIe spec r3.1, sec 7.8.6, the L0s Exit Latency is only valid when L0s
is supported, and similarly the L1 Exit Latency is only valid when L1 is
s

lspci: Decode only supported ASPM exit latencies

Per PCIe spec r3.1, sec 7.8.6, the L0s Exit Latency is only valid when L0s
is supported, and similarly the L1 Exit Latency is only valid when L1 is
supported.

Only decode the L0s and L1 Exit Latencies if they are defined.

For example, on a device that supports L1 but not L0s, the difference in
the "lspci -vv" output looks like this:

- LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L0s <1us, L1 <16us
+ LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L1 <16us

Correct the comments on the PCI_EXP_LNKCAP_L0S and PCI_EXP_LNKCAP_L1
definitions.

Signed-off-by: Bjorn Helgaas <[email protected]>

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lspci: Decode "Slot Implemented" for PCI/PCI-X to PCIe Bridges

The secondary side of a PCI/PCI-X to PCIe Bridge (a "reverse bridge") is a
PCIe Downstream Port and could support a slot just like Root

lspci: Decode "Slot Implemented" for PCI/PCI-X to PCIe Bridges

The secondary side of a PCI/PCI-X to PCIe Bridge (a "reverse bridge") is a
PCIe Downstream Port and could support a slot just like Root Ports and
Switch Downstream Ports.

Decode "Slot Implemented" for reverse bridges and, if true, the Slot
Capabilities, Control, and Status registers.

For a reverse bridge with no slot, the difference in the "lspci -vv" output
looks like this:

- Capabilities: [40] Express (v2) PCI/PCI-X to PCI-Express Bridge, MSI 00
+ Capabilities: [40] Express (v2) PCI/PCI-X to PCI-Express Bridge (Slot-), MSI 00

Signed-off-by: Bjorn Helgaas <[email protected]>

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