pcilmr: Fix margining for ports with Lane reversal

Current implementation interacts only with first Negotiated Link Width
lanes even when Maximum Link Width for the port is bigger than that and
Lane

pcilmr: Fix margining for ports with Lane reversal

Current implementation interacts only with first Negotiated Link Width
lanes even when Maximum Link Width for the port is bigger than that and
Lane reversal is used. Utility in such situation may try to margin lane
which is not used right now and erroneously fail with
'Error during caps reading' message. Fix that behaviour.

Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Apply grading quirk for Ice Lake RC ports

Ice Lake RC ports don't support two side independent timing margining,
however the entire margin across the eye is what is reported by one side
marg

pcilmr: Apply grading quirk for Ice Lake RC ports

Ice Lake RC ports don't support two side independent timing margining,
however the entire margin across the eye is what is reported by one side
margining. Utility already has quirks for Ice Lake RC, so expand them
based on this grading information.

Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Add option to configure margining dwell time

Signed-off-by: Nikita Proshkin <[email protected]>

pcilmr: Move most of pcilmr arguments parsing logic to the separate file

Also change arguments parsing logic: now link parameters (selected lane
numbers, timing or voltage steps, etc) need to be spe

pcilmr: Move most of pcilmr arguments parsing logic to the separate file

Also change arguments parsing logic: now link parameters (selected lane
numbers, timing or voltage steps, etc) need to be specified after link port
and will affect only this link margining (previously, one option was
applied to all links).

See updated man for syntax and example.

Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Add handling of situations when device reports its MaxOffset values equal to 0

According to spec, for the MaxTimingOffset and MaxVoltageOffset parameters
'A 0 value may be reported if the ve

pcilmr: Add handling of situations when device reports its MaxOffset values equal to 0

According to spec, for the MaxTimingOffset and MaxVoltageOffset parameters
'A 0 value may be reported if the vendor chooses not to report the offset'.

Use max possible Offset value in such situations and report to the user.

Reviewed-by: Sergei Miroshnichenko <[email protected]>
Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Add support for unique hardware quirks

Make it possible to change receiver margining parameters depending on
current hardware specificity.

In our tests Intel Ice Lake CPUs RC ports reported

pcilmr: Add support for unique hardware quirks

Make it possible to change receiver margining parameters depending on
current hardware specificity.

In our tests Intel Ice Lake CPUs RC ports reported
MaxVoltageOffset = 50 (RxA), which led to results several times bigger
than the results of the hardware debugger.
Looks like in Intel Sapphire Rapids this was fixed, these CPU RC ports
report MaxVoltageOffset = 12 (RxA). To solve the problem it was decided
to hardcode Volt Offset to 12 (120 mV) for Ice Lake RC ports.

In the case of margining a specific link, only information about
Downstream and Upstream ports should be sufficient to decide whether to
use quirks, so the feature was implemented based on a list of devices
(vendor - device - revision triples), whose problems are known.

Back to Ice Lake ports, according to Integrators List on the pci-sig site,
the list of possible RC ports of Ice Lake Xeon's includes at least three
more options (with ids 347B/C/D) besides the one used in this commit, but
we don't have such processors to check the relevance of the MaxVoltageOffset
problem for these ports.

Reviewed-by: Sergei Miroshnichenko <[email protected]>
Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Add logging functions for margining

* Implement option to turn on/off logging for margining;
* Support systems with several PCI domains;
* margin_log_margining function prints margining in p

pcilmr: Add logging functions for margining

* Implement option to turn on/off logging for margining;
* Support systems with several PCI domains;
* margin_log_margining function prints margining in progress log using
one line messages for each Receiver in the form:
"Margining - <direction> - Lanes [<current simultaneous lanes>] - ETA:
<current direction-lanes margining remaining time> Steps: <current
margining steps done> Total ETA: <utility run total remaining time>".

Reviewed-by: Sergei Miroshnichenko <[email protected]>
Signed-off-by: Nikita Proshkin <[email protected]>

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