LMR: <string.h> is required for memset()

pcilmr: Fix margining for ports with Lane reversal

Current implementation interacts only with first Negotiated Link Width
lanes even when Maximum Link Width for the port is bigger than that and
Lane

pcilmr: Fix margining for ports with Lane reversal

Current implementation interacts only with first Negotiated Link Width
lanes even when Maximum Link Width for the port is bigger than that and
Lane reversal is used. Utility in such situation may try to margin lane
which is not used right now and erroneously fail with
'Error during caps reading' message. Fix that behaviour.

Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Update usage and man: new arguments format and grading

Signed-off-by: Nikita Proshkin <[email protected]>

pcilmr: Apply grading quirk for Ice Lake RC ports

Ice Lake RC ports don't support two side independent timing margining,
however the entire margin across the eye is what is reported by one side
marg

pcilmr: Apply grading quirk for Ice Lake RC ports

Ice Lake RC ports don't support two side independent timing margining,
however the entire margin across the eye is what is reported by one side
margining. Utility already has quirks for Ice Lake RC, so expand them
based on this grading information.

Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Add option to configure margining dwell time

Signed-off-by: Nikita Proshkin <[email protected]>

pcilmr: Add new grading option

Original version of the utility used values from the Table 8-11 of the
PCIe Base Spec Rev 5.0 to evaluate lanes. But it seems that these values
relate only to the marg

pcilmr: Add new grading option

Original version of the utility used values from the Table 8-11 of the
PCIe Base Spec Rev 5.0 to evaluate lanes. But it seems that these values
relate only to the margining equipment and are not relevant to evaluating
the quality of connections.

The PCIe Base Spec Rev 5.0 sets the minimum values for the eye in the
section 8.4.2. Change default grading values in the utility according to
this section.

The specification uses the values of the full width and height of the eye,
so add these values to the output of the utility.

In addition, manufacturers can provide criteria for their devices that
differ from the standard ones. Usually this information falls under the
NDA, so add an option to the utility that will allow the user to set
necessary criteria for evaluating the quality of lanes.

Implement the following syntax for the -g(rading) option:
-g 1t=15ps,f | -g 6v=20

Use passed per link receiver criteria for the eye width (timing - t) or
height (voltage - v) in the utility results.

Additional flag f is for situations when port doesn't support two side
independent margining. In such cases by default calculate EW or EH as a
double one side result. User can add f flag for -g option to tell the
utility that the result in one direction is actually the measurement of
the full eye (for example, Ice Lake RC ports work in this way) and it does
not need to be multiplied.

Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Move most of pcilmr arguments parsing logic to the separate file

Also change arguments parsing logic: now link parameters (selected lane
numbers, timing or voltage steps, etc) need to be spe

pcilmr: Move most of pcilmr arguments parsing logic to the separate file

Also change arguments parsing logic: now link parameters (selected lane
numbers, timing or voltage steps, etc) need to be specified after link port
and will affect only this link margining (previously, one option was
applied to all links).

See updated man for syntax and example.

Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Ensure that utility can accept either Downstream or Upstream link port

Previously, the utility expected only the Upstream Port to be input and,
in fact, passing the Downstream Port led to st

pcilmr: Ensure that utility can accept either Downstream or Upstream link port

Previously, the utility expected only the Upstream Port to be input and,
in fact, passing the Downstream Port led to strange and buggy error
messages. Improve arguments parsing logic to accept any side of the link.

It seems that the only use case that will not be available now is margining
the internal links of the switch, but this scenario looks as strange as
possible.

Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Fix compilation for windows and djgpp

pcilmr: Avoid strftime with %F and produce proper ISO 8601 time

%F is not portable.

pcilmr: Clean up includes

bitops.h moved to root

It is a part of the utilities, not of libpci.

bitops.h should not be included from public pci.h

pcilmr: Add handling of situations when device reports its MaxOffset values equal to 0

According to spec, for the MaxTimingOffset and MaxVoltageOffset parameters
'A 0 value may be reported if the ve

pcilmr: Add handling of situations when device reports its MaxOffset values equal to 0

According to spec, for the MaxTimingOffset and MaxVoltageOffset parameters
'A 0 value may be reported if the vendor chooses not to report the offset'.

Use max possible Offset value in such situations and report to the user.

Reviewed-by: Sergei Miroshnichenko <[email protected]>
Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Add option to save margining results in csv form

Reviewed-by: Sergei Miroshnichenko <[email protected]>
Signed-off-by: Nikita Proshkin <[email protected]>

pcilmr: Add support for unique hardware quirks

Make it possible to change receiver margining parameters depending on
current hardware specificity.

In our tests Intel Ice Lake CPUs RC ports reported

pcilmr: Add support for unique hardware quirks

Make it possible to change receiver margining parameters depending on
current hardware specificity.

In our tests Intel Ice Lake CPUs RC ports reported
MaxVoltageOffset = 50 (RxA), which led to results several times bigger
than the results of the hardware debugger.
Looks like in Intel Sapphire Rapids this was fixed, these CPU RC ports
report MaxVoltageOffset = 12 (RxA). To solve the problem it was decided
to hardcode Volt Offset to 12 (120 mV) for Ice Lake RC ports.

In the case of margining a specific link, only information about
Downstream and Upstream ports should be sufficient to decide whether to
use quirks, so the feature was implemented based on a list of devices
(vendor - device - revision triples), whose problems are known.

Back to Ice Lake ports, according to Integrators List on the pci-sig site,
the list of possible RC ports of Ice Lake Xeon's includes at least three
more options (with ids 347B/C/D) besides the one used in this commit, but
we don't have such processors to check the relevance of the MaxVoltageOffset
problem for these ports.

Reviewed-by: Sergei Miroshnichenko <[email protected]>
Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Add function for default margining results log

Lanes are rated according to the minimum/recommended values.
The minimum values are taken from PCIe Base Spec Rev 5.0 section 8.4.4.
30% UI rec

pcilmr: Add function for default margining results log

Lanes are rated according to the minimum/recommended values.
The minimum values are taken from PCIe Base Spec Rev 5.0 section 8.4.4.
30% UI recommended value for timing is taken from NVIDIA presentation
"PCIe 4.0 Mass Electrical Margins Data Collection".

Receiver lanes are called 'Weird' if all results of all receiver lanes
are equal to the spec minimum value.

Reviewed-by: Sergei Miroshnichenko <[email protected]>
Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Add logging functions for margining

* Implement option to turn on/off logging for margining;
* Support systems with several PCI domains;
* margin_log_margining function prints margining in p

pcilmr: Add logging functions for margining

* Implement option to turn on/off logging for margining;
* Support systems with several PCI domains;
* margin_log_margining function prints margining in progress log using
one line messages for each Receiver in the form:
"Margining - <direction> - Lanes [<current simultaneous lanes>] - ETA:
<current direction-lanes margining remaining time> Steps: <current
margining steps done> Total ETA: <utility run total remaining time>".

Reviewed-by: Sergei Miroshnichenko <[email protected]>
Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Add margining process functions

* Implement the margining flow as described in the section "Example
Software Flow for Lane Margining at Receiver"
of the PCIe Base Spec Rev 5.0;
* Impleme

pcilmr: Add margining process functions

* Implement the margining flow as described in the section "Example
Software Flow for Lane Margining at Receiver"
of the PCIe Base Spec Rev 5.0;
* Implement margining commands formation and response parsing according
to the PCIe Base Spec Rev 5.0 table 4-26;
* Use Receiver margining parameters as described in the
PCIe Base Spec Rev 5.0 table 8-11;
* Support lane reversal and simultaneous margining of several link lanes.

Reviewed-by: Sergei Miroshnichenko <[email protected]>
Signed-off-by: Nikita Proshkin <[email protected]>

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pcilmr: Add functions for device checking and preparations before main margining processes

Follow the checklist from PCIe Base Spec Rev 5.0 section 4.2.13.3
"Receiver Margin Testing Requirements":
*

pcilmr: Add functions for device checking and preparations before main margining processes

Follow the checklist from PCIe Base Spec Rev 5.0 section 4.2.13.3
"Receiver Margin Testing Requirements":
* Verify the Link is at 16 GT/s or higher data rate, in DO PM state;
* Verify that Margining Ready bit of the device is set;
* Disable the ASPM and Autonomous Speed/Width features for the duration
of the test.

Also verify that Upstream Port of the Link is Function 0 of a Device,
according to spec, only it must implement margining registers.

Reviewed-by: Sergei Miroshnichenko <[email protected]>
Signed-off-by: Nikita Proshkin <[email protected]>

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