Reduce verbiage of lit.local.cfg filesWe can just split targets_to_build in one place and make it immutable.llvm-svn: 210496
[tests] Cleanup initialization of test suffixes. - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a
[tests] Cleanup initialization of test suffixes. - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a few suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py). - Aside from removing the need for a bunch of lit.local.cfg files, this enables 4 tests that were inadvertently being skipped (one in Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been XFAILED). - This commit also fixes a bunch of config files to use config.root instead of older copy-pasted code.llvm-svn: 188513
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[XCore] Add LDAPB instructions.With the change the disassembler now supports the XCore ISA in itsentirety.llvm-svn: 181155
[XCore] Add BLRB instructions.llvm-svn: 181152
Use object file specific section type for initial text sectionllvm-svn: 179494
[XCore] Add bru instruction.llvm-svn: 178783
[XCore] The RRegs register class is a superset of GRRegs.At the time when the XCore backend was added there were some issues withwith overlapping register classes but these all seem to be fixed no
[XCore] The RRegs register class is a superset of GRRegs.At the time when the XCore backend was added there were some issues withwith overlapping register classes but these all seem to be fixed now.Describing the register classes correctly allow us to get rid of acodegen only instruction (LDAWSP_lru6_RRegs) and it means we candisassemble ru6 instructions that use registers above r11.llvm-svn: 178782
[XCore] Check disassembly of the st8 instruction.llvm-svn: 178689
[XCore] Update disassembler test to improve coverage of the instructions.Previously some instructions were unintentionally covered twice andothers were not covered at all.llvm-svn: 178688
[XCore] Add missing 2r instructions.These instructions are not targeted by the compiler but it is needed forthe MC layer.llvm-svn: 175407
[XCore] Add TSETR instruction.This instruction is not targeted by the compiler but it is needed for theMC layer.llvm-svn: 175406
[XCore] Add missing u10 / lu10 instructions.These instructions are not targeted by the compiler but they areneeded for the MC layer.llvm-svn: 175404
[XCore] Add missing u6 / lu6 instructions.These instructions are not targeted by the compiler but they areneeded for the MC layer.llvm-svn: 175403
[XCore] Add missing l2rus instructions.These instructions are not targeted by the compiler but they areneeded for the MC layer.llvm-svn: 173634
[XCore] Add missing l2r instructions.These instructions are not targeted by the compiler but they areneeded for the MC layer.llvm-svn: 173629
[XCore] Add missing 1r instructions.These instructions are not targeted by the compiler but they areneeded for the MC layer.llvm-svn: 173624
[XCore] Add missing 0r instructions.These instructions are not targeted by the compiler but they areneeded for the MC layer.llvm-svn: 173623
Add instruction encodings / disassembly support for l4r instructions.llvm-svn: 173501
Add instruction encodings / disassembly support for l5r instructions.llvm-svn: 173479
Add instruction encodings / disassembly support for l6r instructions.llvm-svn: 173288
Add instruction encodings / disassembly support for u10 / lu10 instructions.llvm-svn: 173204
Add instruction encodings / disassembly support for u6 / lu6 instructions.llvm-svn: 173086
Add instruction encoding / disassembly support for ru6 / lru6 instructions.llvm-svn: 173085
Add instruction encodings / disassembly support for l2rus instructions.llvm-svn: 172987
Add instruction encodings / disassembly support for l3r instructions.llvm-svn: 172986
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