History log of /llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/simd-offset.ll (Results 1 – 23 of 23)
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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3
# fec47492 01-Sep-2021 Thomas Lively <[email protected]>

[WebAssembly] Lower v2f32 to v2f64 extending loads with promote_low

Previously extra wide v4f32 to v4f64 extending loads would be legalized to v2f32
to v2f64 extending loads, which would then be sca

[WebAssembly] Lower v2f32 to v2f64 extending loads with promote_low

Previously extra wide v4f32 to v4f64 extending loads would be legalized to v2f32
to v2f64 extending loads, which would then be scalarized by legalization. (v2f32
to v2f64 extending loads not produced by legalization were already being emitted
correctly.) Instead, mark v2f32 to v2f64 extending loads as legal and explicitly
lower them using promote_low. This regresses the addressing modes supported for
the extloads not produced by legalization, but that's a fine trade off for now.

Differential Revision: https://reviews.llvm.org/D108496

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Revision tags: llvmorg-13.0.0-rc2
# b69374ca 19-Aug-2021 Thomas Lively <[email protected]>

[WebAssembly] Legalize vector types by widening

The default legalization of unsupported vector types is to promote the integers
in each lane, which leads to extra sign or zero extending and masking

[WebAssembly] Legalize vector types by widening

The default legalization of unsupported vector types is to promote the integers
in each lane, which leads to extra sign or zero extending and masking when
moving data into and out of vectors. Switch our preferred type legalization from
the default to vector widening, which keeps the data in the low lanes of the
vector rather than in the low bits of each lane. The unused high lanes can be
ignored.

Half-wide vectors are now loaded from memory into the low 64 bits of the v128
rather than spread out among the lanes. As a result, v128.load64_splat is a much
more common operation, so add new patterns to support it.

Differential Revision: https://reviews.llvm.org/D107502

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Revision tags: llvmorg-13.0.0-rc1, llvmorg-14-init
# 122b0220 14-Jul-2021 Thomas Lively <[email protected]>

[WebAssembly] Remove datalayout strings from llc tests

The data layout strings do not have any effect on llc tests and will become
misleadingly out of date as we continue to update the canonical dat

[WebAssembly] Remove datalayout strings from llc tests

The data layout strings do not have any effect on llc tests and will become
misleadingly out of date as we continue to update the canonical data layout, so
remove them from the tests.

Differential Revision: https://reviews.llvm.org/D105842

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Revision tags: llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1
# e657c84f 19-Apr-2021 Thomas Lively <[email protected]>

[WebAssembly] Use v128.const instead of splats for constants

We previously used splats instead of v128.const to materialize vector constants
because V8 did not support v128.const. Now that V8 suppor

[WebAssembly] Use v128.const instead of splats for constants

We previously used splats instead of v128.const to materialize vector constants
because V8 did not support v128.const. Now that V8 supports v128.const, we can
use v128.const instead. Although this increases code size, it should also
increase performance (or at least require fewer engine-side optimizations), so
it is an appropriate change to make.

Differential Revision: https://reviews.llvm.org/D100716

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Revision tags: llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1
# a781a706 22-Dec-2020 Thomas Lively <[email protected]>

[WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats

These instructions previously used prefixes like v8x16 to signify that they were
agnostic between float and int interpretations. We renam

[WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats

These instructions previously used prefixes like v8x16 to signify that they were
agnostic between float and int interpretations. We renamed these instructions to
remove this form of prefix in https://github.com/WebAssembly/simd/issues/297 and
https://github.com/WebAssembly/simd/issues/316 and this commit brings the names
in LLVM up to date.

Differential Revision: https://reviews.llvm.org/D93722

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Revision tags: llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2
# ffd8c23c 29-Jul-2020 Thomas Lively <[email protected]>

[WebAssembly] Implement truncating vector stores

Rather than expanding truncating stores so that vectors are stored one
lane at a time, lower them to a sequence of instructions using
narrowing opera

[WebAssembly] Implement truncating vector stores

Rather than expanding truncating stores so that vectors are stored one
lane at a time, lower them to a sequence of instructions using
narrowing operations instead, when possible. Since the narrowing
operations have saturating semantics, but truncating stores require
truncation, mask the stored value to manually truncate it before
narrowing. Also, since narrowing is a binary operation, pass in the
original vector as the unused second argument.

Differential Revision: https://reviews.llvm.org/D84377

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Revision tags: llvmorg-11.0.0-rc1
# a4594592 23-Jul-2020 Thomas Lively <[email protected]>

[WebAssembly] Fix store_unfolded_offset tests in simd-offset.ll

These tests were previously duplicates of the
unfolded_gep_negative_offset tests, and this change updates them to
test what they were

[WebAssembly] Fix store_unfolded_offset tests in simd-offset.ll

These tests were previously duplicates of the
unfolded_gep_negative_offset tests, and this change updates them to
test what they were meant to test.

Differential Revision: https://reviews.llvm.org/D84365

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# 51cd326f 22-Jul-2020 Thomas Lively <[email protected]>

[WebAssembly] Autogenerate checks in simd-offset.ll

Implementing new functionality tested in this file requires adding new
tests for many IR addressing patterns, which can be a large
maintenance bur

[WebAssembly] Autogenerate checks in simd-offset.ll

Implementing new functionality tested in this file requires adding new
tests for many IR addressing patterns, which can be a large
maintenance burden. This patch makes adding tests easier by switching
to using autogenerated checks. This patch also removes the testing
mode that has simd128 disabled because it would produce very large
checks and is not particularly interesting.

Differential Revision: https://reviews.llvm.org/D84288

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Revision tags: llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2, llvmorg-10.0.1-rc1
# c702d4bf 15-May-2020 Thomas Lively <[email protected]>

[WebAssembly] Update latest implemented SIMD instructions

Summary:
Move instructions that have recently been implemented in V8 from the
`unimplemented-simd128` target feature to the `simd128` target

[WebAssembly] Update latest implemented SIMD instructions

Summary:
Move instructions that have recently been implemented in V8 from the
`unimplemented-simd128` target feature to the `simd128` target
feature. The updated instructions match the update at
https://github.com/WebAssembly/simd/pull/223.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D79973

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Revision tags: llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3, llvmorg-10.0.0-rc2
# 27748363 31-Jan-2020 Thomas Lively <[email protected]>

[WebAssembly] Enable recently implemented SIMD operations

Summary:
Moves a batch of instructions from unimplemented-simd128 to simd128
because they have recently become available in V8.

Reviewers:

[WebAssembly] Enable recently implemented SIMD operations

Summary:
Moves a batch of instructions from unimplemented-simd128 to simd128
because they have recently become available in V8.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D73926

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Revision tags: llvmorg-10.0.0-rc1, llvmorg-11-init, llvmorg-9.0.1, llvmorg-9.0.1-rc3, llvmorg-9.0.1-rc2, llvmorg-9.0.1-rc1
# 81125f73 27-Sep-2019 Thomas Lively <[email protected]>

[WebAssembly] SIMD Load and extend operations

Summary:
As specified at
https://github.com/webassembly/simd/blob/master/proposals/simd/SIMD.md#load-and-extend.
These instructions are behind the unimp

[WebAssembly] SIMD Load and extend operations

Summary:
As specified at
https://github.com/webassembly/simd/blob/master/proposals/simd/SIMD.md#load-and-extend.
These instructions are behind the unimplemented-simd128 target feature
for now because they have not been implemented in V8 yet.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68058

llvm-svn: 373040

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# 99d3dd28 23-Sep-2019 Thomas Lively <[email protected]>

[WebAssembly] vNxM.load_splat instructions

Summary:
Adds the new load_splat instructions as specified at
https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#load-and-splat.

DAGIS

[WebAssembly] vNxM.load_splat instructions

Summary:
Adds the new load_splat instructions as specified at
https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#load-and-splat.

DAGISel does not allow matching multiple copies of the same load in a
single pattern, so we use a new node in WebAssemblyISD to wrap loads
that should be splatted.

Depends on D67783.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67784

llvm-svn: 372655

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Revision tags: llvmorg-9.0.0, llvmorg-9.0.0-rc6, llvmorg-9.0.0-rc5, llvmorg-9.0.0-rc4, llvmorg-9.0.0-rc3, llvmorg-9.0.0-rc2, llvmorg-9.0.0-rc1, llvmorg-10-init, llvmorg-8.0.1, llvmorg-8.0.1-rc4, llvmorg-8.0.1-rc3, llvmorg-8.0.1-rc2, llvmorg-8.0.1-rc1, llvmorg-8.0.0, llvmorg-8.0.0-rc5, llvmorg-8.0.0-rc4, llvmorg-8.0.0-rc3, llvmorg-7.1.0, llvmorg-7.1.0-rc1, llvmorg-8.0.0-rc2, llvmorg-8.0.0-rc1
# 64a39a1c 10-Jan-2019 Thomas Lively <[email protected]>

[WebAssembly] Add unimplemented-simd128 subtarget feature

Summary:
This is a third attempt, but this time we have vetted it on Windows
first. The previous errors were due to an uninitialized class m

[WebAssembly] Add unimplemented-simd128 subtarget feature

Summary:
This is a third attempt, but this time we have vetted it on Windows
first. The previous errors were due to an uninitialized class member.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, sunfish, jfb, llvm-commits

Differential Revision: https://reviews.llvm.org/D56560

llvm-svn: 350901

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# fdd4999b 10-Jan-2019 Thomas Lively <[email protected]>

Revert "[WebAssembly] Add simd128-unimplemented subtarget feature"

This reverts rL350791.

llvm-svn: 350795


# eb6f9abd 10-Jan-2019 Thomas Lively <[email protected]>

[WebAssembly] Add simd128-unimplemented subtarget feature

This is a second attempt at r350778, which was reverted in
r350789. The only change is that the unimplemented-simd128 feature has
been renam

[WebAssembly] Add simd128-unimplemented subtarget feature

This is a second attempt at r350778, which was reverted in
r350789. The only change is that the unimplemented-simd128 feature has
been renamed simd128-unimplemented, since naming it
unimplemented-simd128 somehow made the simd128 feature flag enable the
unimplemented-simd128 feature on Windows.

llvm-svn: 350791

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# fdca5fab 10-Jan-2019 Thomas Lively <[email protected]>

Revert "[WebAssembly] Add unimplemented-simd128 subtarget feature"

This reverts L350778.

llvm-svn: 350789


# 2eeade18 09-Jan-2019 Thomas Lively <[email protected]>

[WebAssembly] Add unimplemented-simd128 subtarget feature

Summary:
This replaces the old ad-hoc -wasm-enable-unimplemented-simd
flag. Also makes the new unimplemented-simd128 feature imply the
simd1

[WebAssembly] Add unimplemented-simd128 subtarget feature

Summary:
This replaces the old ad-hoc -wasm-enable-unimplemented-simd
flag. Also makes the new unimplemented-simd128 feature imply the
simd128 feature.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits, alexcrichton

Differential Revision: https://reviews.llvm.org/D56501

llvm-svn: 350778

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# b6dac89c 21-Dec-2018 Thomas Lively <[email protected]>

[WebAssembly] Fix invalid machine instrs in -O0, verify in tests

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llv

[WebAssembly] Fix invalid machine instrs in -O0, verify in tests

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D55956

llvm-svn: 349889

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Revision tags: llvmorg-7.0.1, llvmorg-7.0.1-rc3
# 49482f82 19-Nov-2018 Wouter van Oortmerssen <[email protected]>

[WebAssembly] replaced .param/.result by .functype

Summary:
This makes it easier/cleaner to generate a single signature from
this directive. Also:
- Adds the symbol name, such that we don't depend o

[WebAssembly] replaced .param/.result by .functype

Summary:
This makes it easier/cleaner to generate a single signature from
this directive. Also:
- Adds the symbol name, such that we don't depend on the location
of this directive anymore.
- Actually constructs the signature in the assembler, and make the
assembler own it.
- Refactor the use of MVT vs ValType in the streamer and assembler
to require less conversions overall.
- Changed 700 or so tests to use it.

Reviewers: sbc100, dschuff

Subscribers: jgravelle-google, eraman, aheejin, sunfish, jfb, llvm-commits

Differential Revision: https://reviews.llvm.org/D54652

llvm-svn: 347228

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Revision tags: llvmorg-7.0.1-rc2, llvmorg-7.0.1-rc1
# b61232ea 31-Oct-2018 Thomas Lively <[email protected]>

[WebAssembly] Process p2align operands for SIMD loads and stores

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llv

[WebAssembly] Process p2align operands for SIMD loads and stores

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D53886

llvm-svn: 345795

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# 66f3dc03 15-Sep-2018 Thomas Lively <[email protected]>

[WebAssembly][NFC] Generalize operand numbers in SIMD tests

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org

[WebAssembly][NFC] Generalize operand numbers in SIMD tests

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52130

llvm-svn: 342303

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# a3937b23 14-Sep-2018 Thomas Lively <[email protected]>

[WebAssembly][NFC] Move SIMD encoding tests to dedicated file

Summary:
This change makes the tests more focused and avoids problematic
interactions between the testing modes and instruction encoding

[WebAssembly][NFC] Move SIMD encoding tests to dedicated file

Summary:
This change makes the tests more focused and avoids problematic
interactions between the testing modes and instruction encoding. This
change also allows the other tests to use less verbose output and
stricter checks.

Reviewers: aheejin, dschuff, aardappel

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52007

llvm-svn: 342287

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# e1f67a8b 14-Sep-2018 Thomas Lively <[email protected]>

[WebAssembly][NFC] Fix unconventional test names

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52110

ll

[WebAssembly][NFC] Fix unconventional test names

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52110

llvm-svn: 342273

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