[WebAssembly] Add new target feature in support of 'extended-const' proposal

We don't yet do anything when this feature is enabled, this change
just lays the ground work by accepting that there is s

[WebAssembly] Add new target feature in support of 'extended-const' proposal

We don't yet do anything when this feature is enabled, this change
just lays the ground work by accepting that there is such a feature.

See https://github.com/WebAssembly/extended-const

Differential Revision: https://reviews.llvm.org/D121151

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[WebAssembly] Add relaxed-simd feature

This currently only defines a constant, but it the future will be used
to gate builtins for experimenting and prototyping relaxed-simd proposal
(https://github

[WebAssembly] Add relaxed-simd feature

This currently only defines a constant, but it the future will be used
to gate builtins for experimenting and prototyping relaxed-simd proposal
(https://github.com/WebAssembly/relaxed-simd/).

Differential Revision: https://reviews.llvm.org/D110111

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[WebAssembly] Remove unimplemented-simd target feature

Now that the WebAssembly SIMD specification is finalized and engines are
generally up-to-date, there is no need for a separate target feature f

[WebAssembly] Remove unimplemented-simd target feature

Now that the WebAssembly SIMD specification is finalized and engines are
generally up-to-date, there is no need for a separate target feature for gating
SIMD instructions that engines have not implemented. With this change,
v128.const is now enabled by default with the simd128 target feature.

Differential Revision: https://reviews.llvm.org/D98457

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[X86][MC][Target] Initial backend support a tune CPU to support -mtune

This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute

[X86][MC][Target] Initial backend support a tune CPU to support -mtune

This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute is not present X86 will use the resolved CPU from target-cpu attribute or command line.

This patch adds MC layer support a tune CPU. Each CPU now has two sets of features stored in their GenSubtargetInfo.inc tables . These features lists are passed separately to the Processor and ProcessorModel classes in tablegen. The tune list defaults to an empty list to avoid changes to non-X86. This annoyingly increases the size of static tables on all target as we now store 24 more bytes per CPU. I haven't quantified the overall impact, but I can if we're concerned.

One new test is added to X86 to show a few tuning features with mismatched tune-cpu and target-cpu/target-feature attributes to demonstrate independent control. Another new test is added to demonstrate that the scheduler model follows the tune CPU.

I have not added a -mtune to llc/opt or MC layer command line yet. With no attributes we'll just use the -mcpu for both. MC layer tools will always follow the normal CPU for tuning.

Differential Revision: https://reviews.llvm.org/D85165

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[WebAssembly] Minor cleanup to WebAssemblySubtarget. NFC.

Pretty much all other platforms pass CPU string as arg0 of
initializeSubtargetDependencies.

Differential Revision: https://reviews.llvm.org

[WebAssembly] Minor cleanup to WebAssemblySubtarget. NFC.

Pretty much all other platforms pass CPU string as arg0 of
initializeSubtargetDependencies.

Differential Revision: https://reviews.llvm.org/D77894

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[WebAssembly] Add reference types target feature

Summary:
This adds the reference types target feature. This does not enable any
more functionality in LLVM/clang for now, but this is necessary to em

[WebAssembly] Add reference types target feature

Summary:
This adds the reference types target feature. This does not enable any
more functionality in LLVM/clang for now, but this is necessary to embed
the info in the target features section, which is used by Binaryen and
Emscripten. It turned out that after D69832 `-fwasm-exceptions` crashed
because we didn't have the reference types target feature.

Reviewers: tlively

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D73320

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[WebAssembly] Enable IndirectBrExpandPass

Wasm doesn't have a direct way to lower indirectbr, so hook up the
IndirectBrExpandPass to lower indirectbr into a switch.

Fixes PR42498

Reviewers: aheeji

[WebAssembly] Enable IndirectBrExpandPass

Wasm doesn't have a direct way to lower indirectbr, so hook up the
IndirectBrExpandPass to lower indirectbr into a switch.

Fixes PR42498

Reviewers: aheejin

Differential Revision: https://reviews.llvm.org/D64161

llvm-svn: 365096

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[WebAssembly] Add multivalue and tail-call target features

Summary:
These features will both be implemented soon, so I thought I would
save time by adding the boilerplate for both of them at the sam

[WebAssembly] Add multivalue and tail-call target features

Summary:
These features will both be implemented soon, so I thought I would
save time by adding the boilerplate for both of them at the same time.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D62047

llvm-svn: 361516

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[WebAssembly] Add mutable globals feature

Summary:
This feature is not actually used for anything in the WebAssembly
backend, but adding it allows users to get it into the target features
sections o

[WebAssembly] Add mutable globals feature

Summary:
This feature is not actually used for anything in the WebAssembly
backend, but adding it allows users to get it into the target features
sections of their objects, which makes these objects
future-compatible.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jdoerfert, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D60013

llvm-svn: 357321

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[WebAssembly] Merge used feature sets, update atomics linkage policy

Summary:
It does not currently make sense to use WebAssembly features in some functions
but not others, so this CL adds an IR pas

[WebAssembly] Merge used feature sets, update atomics linkage policy

Summary:
It does not currently make sense to use WebAssembly features in some functions
but not others, so this CL adds an IR pass that takes the union of all used
feature sets and applies it to each function in the module. This allows us to
prevent atomics from being lowered away if some function has opted in to using
them. When atomics is not enabled anywhere, we detect whether there exists any
atomic operations or thread local storage that would be stripped and disallow
linking with objects that contain atomics if and only if atomics or tls are
stripped. When atomics is enabled, mark it as used but do not require it of
other objects in the link. These changes allow libraries that do not use atomics
to be built once and linked into both single-threaded and multithreaded
binaries.

Reviewers: aheejin, sbc100, dschuff

Subscribers: jgravelle-google, hiraditya, sunfish, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59625

llvm-svn: 357226

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[WebAssembly] Add bulk memory target feature

Summary: Also clean up some preexisting target feature code.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, jfb

[WebAssembly] Add bulk memory target feature

Summary: Also clean up some preexisting target feature code.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, jfb

Differential Revision: https://reviews.llvm.org/D57495

llvm-svn: 352793

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Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the ne

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636

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[WebAssembly] Add unimplemented-simd128 subtarget feature

Summary:
This is a third attempt, but this time we have vetted it on Windows
first. The previous errors were due to an uninitialized class m

[WebAssembly] Add unimplemented-simd128 subtarget feature

Summary:
This is a third attempt, but this time we have vetted it on Windows
first. The previous errors were due to an uninitialized class member.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, sunfish, jfb, llvm-commits

Differential Revision: https://reviews.llvm.org/D56560

llvm-svn: 350901

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Revert "[WebAssembly] Add simd128-unimplemented subtarget feature"

This reverts rL350791.

llvm-svn: 350795

[WebAssembly] Add simd128-unimplemented subtarget feature

This is a second attempt at r350778, which was reverted in
r350789. The only change is that the unimplemented-simd128 feature has
been renam

[WebAssembly] Add simd128-unimplemented subtarget feature

This is a second attempt at r350778, which was reverted in
r350789. The only change is that the unimplemented-simd128 feature has
been renamed simd128-unimplemented, since naming it
unimplemented-simd128 somehow made the simd128 feature flag enable the
unimplemented-simd128 feature on Windows.

llvm-svn: 350791

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Revert "[WebAssembly] Add unimplemented-simd128 subtarget feature"

This reverts L350778.

llvm-svn: 350789

[WebAssembly] Add unimplemented-simd128 subtarget feature

Summary:
This replaces the old ad-hoc -wasm-enable-unimplemented-simd
flag. Also makes the new unimplemented-simd128 feature imply the
simd1

[WebAssembly] Add unimplemented-simd128 subtarget feature

Summary:
This replaces the old ad-hoc -wasm-enable-unimplemented-simd
flag. Also makes the new unimplemented-simd128 feature imply the
simd128 feature.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits, alexcrichton

Differential Revision: https://reviews.llvm.org/D56501

llvm-svn: 350778

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Remove \brief commands from doxygen comments.

We've been running doxygen with the autobrief option for a couple of
years now. This makes the \brief markers into our comments
redundant. Since they ar

Remove \brief commands from doxygen comments.

We've been running doxygen with the autobrief option for a couple of
years now. This makes the \brief markers into our comments
redundant. Since they are a visual distraction and we don't want to
encourage more \brief markers in new code either, this patch removes
them all.

Patch produced by

for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done

Differential Revision: https://reviews.llvm.org/D46290

llvm-svn: 331272

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[WebAssembly] Add exception handling option and feature

Summary:
Add a llc command line option and WebAssembly architecture feature for
exception handling.

Reviewers: dschuff

Subscribers: jfb, sbc

[WebAssembly] Add exception handling option and feature

Summary:
Add a llc command line option and WebAssembly architecture feature for
exception handling.

Reviewers: dschuff

Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D43683

llvm-svn: 326004

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[WebAssembly] Make sign-extension opcodes a distinct feature.

Sign-extension opcodes have been split into a separate proposal from
the main threads proposal, so switch them to their own target
featu

[WebAssembly] Make sign-extension opcodes a distinct feature.

Sign-extension opcodes have been split into a separate proposal from
the main threads proposal, so switch them to their own target
feature. See:

https://github.com/WebAssembly/sign-extension-ops

llvm-svn: 322966

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[WebAssembly] Fix trapping behavior in fptosi/fptoui.

This adds code to protect WebAssembly's `trunc_s` family of opcodes
from values outside their domain. Even though such conversions have
full und

[WebAssembly] Fix trapping behavior in fptosi/fptoui.

This adds code to protect WebAssembly's `trunc_s` family of opcodes
from values outside their domain. Even though such conversions have
full undefined behavior in C/C++, LLVM IR's `fptosi` and `fptoui` do
not, and only return undef.

This also implements the proposed non-trapping float-to-int conversion
feature and uses that instead when available.

llvm-svn: 319128

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Fix a bunch more layering of CodeGen headers that are in Target

All these headers already depend on CodeGen headers so moving them into
CodeGen fixes the layering (since CodeGen depends on Target, n

Fix a bunch more layering of CodeGen headers that are in Target

All these headers already depend on CodeGen headers so moving them into
CodeGen fixes the layering (since CodeGen depends on Target, not the
other way around).

llvm-svn: 318490

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[WebAssembly] Add target feature for atomics

Summary:
This tracks the WebAssembly threads feature proposal at
https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md

Differ

[WebAssembly] Add target feature for atomics

Summary:
This tracks the WebAssembly threads feature proposal at
https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md

Differential Revision: https://reviews.llvm.org/D37300

llvm-svn: 312145

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[WebAssembly] Move useAA() out of line to make it more convenient to experiment with.

llvm-svn: 254856

WebAssembly: basic bitcode → assembly CodeGen test

Summary:
Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements th

WebAssembly: basic bitcode → assembly CodeGen test

Summary:
Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements the basic needed for the test run to not crash / assert. Getting to that point required:

- Basic InstPrinter.
- Basic AsmPrinter.
- DiagnosticInfoUnsupported (not strictly required, but nice to have, duplicated from AMDGPU/BPF's ISelLowering).
- Some SP and register setup in WebAssemblyTargetLowering.
- Basic LowerFormalArguments.
- GenInstrInfo.
- Placeholder LowerFormalArguments.
- Placeholder CanLowerReturn and LowerReturn.
- Basic DAGToDAGISel::Select, which requiresGenDAGISel.inc as well as GET_INSTRINFO_ENUM with GenInstrInfo.inc.
- Remove WebAssemblyFrameLowering::determineCalleeSaves and rely on default.
- Implement WebAssemblyFrameLowering::hasFP, same as AArch64's implementation.

Follow-up patches will implement a real AsmPrinter, which will require adding MI opcodes specific to WebAssembly.

Reviewers: sunfish

Subscribers: aemerson, jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D11369

llvm-svn: 242939

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