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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init |
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904a87ac |
| 26-Jul-2022 |
Weining Lu <[email protected]> |
[LoongArch] Use `end namespace xxx` style comment. NFC
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3c849d0a |
| 15-Jul-2022 |
Fangrui Song <[email protected]> |
Modernize Optional::{getValueOr,hasValue}
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47f3dc6d |
| 13-Jul-2022 |
gonglingqin <[email protected]> |
[LoongArch] Add codegen support for atomic fence, atomic load and atomic store
Differential Revision: https://reviews.llvm.org/D128901
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Revision tags: llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1 |
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a1c67439 |
| 31-Mar-2022 |
wanglei <[email protected]> |
[LoongArch] Construct codegen infra and generate first add instruction.
This patch constructs codegen infra and successfully generate the first
'add' instruction. Add integer calling convention for
[LoongArch] Construct codegen infra and generate first add instruction.
This patch constructs codegen infra and successfully generate the first
'add' instruction. Add integer calling convention for fixed arguments which
are passed with general-purpose registers.
New test added here:
CodeGen/LoongArch/ir-instruction/add.ll
The test file is placed in a subdirectory because we will use
subdirctories to distinguish different categories of tests (e.g.
intrinsic, inline-asm ...)
Reviewed By: MaskRay, SixWeining
Differential Revision: https://reviews.llvm.org/D122366
show more ...
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Revision tags: llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2 |
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33388ae8 |
| 10-Feb-2022 |
Lu Weining <[email protected]> |
[LoongArch 4/6] Add basic tablegen infra for LoongArch
This patch introduces basic tablegen infra such as
LoongArch{InstrFormats,InstrInfo,RegisterInfo,CallingConv,}.td.
For now, only add instructi
[LoongArch 4/6] Add basic tablegen infra for LoongArch
This patch introduces basic tablegen infra such as
LoongArch{InstrFormats,InstrInfo,RegisterInfo,CallingConv,}.td.
For now, only add instruction definitions for LoongArch basic integer
operations.
Our initial target is a working MC layer rather than codegen,
so appropriate SelectionDAG patterns will come later.
Differential revision: https://reviews.llvm.org/D115861
show more ...
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444c6d26 |
| 10-Feb-2022 |
Lu Weining <[email protected]> |
[LoongArch 3/6] Add target stub for LoongArch
This patch registers the 'loongarch32' and 'loongarch64' targets. Also adds a
simple testcase to check the output of llc --vesion containing the targets
[LoongArch 3/6] Add target stub for LoongArch
This patch registers the 'loongarch32' and 'loongarch64' targets. Also adds a
simple testcase to check the output of llc --vesion containing the targets.
Differential revision: https://reviews.llvm.org/D115860
show more ...
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