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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init |
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3e0bf1c7 |
| 14-Jul-2022 |
David Green <[email protected]> |
[CodeGen] Move instruction predicate verification to emitInstruction
D25618 added a method to verify the instruction predicates for an emitted instruction, through verifyInstructionPredicates added
[CodeGen] Move instruction predicate verification to emitInstruction
D25618 added a method to verify the instruction predicates for an emitted instruction, through verifyInstructionPredicates added into <Target>MCCodeEmitter::encodeInstruction. This is a very useful idea, but the implementation inside MCCodeEmitter made it only fire for object files, not assembly which most of the llvm test suite uses.
This patch moves the code into the <Target>_MC::verifyInstructionPredicates method, inside the InstrInfo. The allows it to be called from other places, such as in this patch where it is called from the <Target>AsmPrinter::emitInstruction methods which should trigger for both assembly and object files. It can also be called from other places such as verifyInstruction, but that is not done here (it tends to catch errors earlier, but in reality just shows all the mir tests that have incorrect feature predicates). The interface was also simplified slightly, moving computeAvailableFeatures into the function so that it does not need to be called externally.
The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currently show errors in the test-suite, so have been disabled with FIXME comments.
Recommitted with some fixes for the leftover MCII variables in release builds.
Differential Revision: https://reviews.llvm.org/D129506
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95252133 |
| 13-Jul-2022 |
David Green <[email protected]> |
Revert "Move instruction predicate verification to emitInstruction"
This reverts commit e2fb8c0f4b940e0285ee36c112469fa75d4b60ff as it does not build for Release builds, and some buildbots are givin
Revert "Move instruction predicate verification to emitInstruction"
This reverts commit e2fb8c0f4b940e0285ee36c112469fa75d4b60ff as it does not build for Release builds, and some buildbots are giving more warning than I saw locally. Reverting to fix those issues.
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e2fb8c0f |
| 13-Jul-2022 |
David Green <[email protected]> |
Move instruction predicate verification to emitInstruction
D25618 added a method to verify the instruction predicates for an emitted instruction, through verifyInstructionPredicates added into <Targ
Move instruction predicate verification to emitInstruction
D25618 added a method to verify the instruction predicates for an emitted instruction, through verifyInstructionPredicates added into <Target>MCCodeEmitter::encodeInstruction. This is a very useful idea, but the implementation inside MCCodeEmitter made it only fire for object files, not assembly which most of the llvm test suite uses.
This patch moves the code into the <Target>_MC::verifyInstructionPredicates method, inside the InstrInfo. The allows it to be called from other places, such as in this patch where it is called from the <Target>AsmPrinter::emitInstruction methods which should trigger for both assembly and object files. It can also be called from other places such as verifyInstruction, but that is not done here (it tends to catch errors earlier, but in reality just shows all the mir tests that have incorrect feature predicates). The interface was also simplified slightly, moving computeAvailableFeatures into the function so that it does not need to be called externally.
The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currently show errors in the test-suite, so have been disabled with FIXME comments.
Differential Revision: https://reviews.llvm.org/D129506
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Revision tags: llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1 |
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989f1c72 |
| 15-Mar-2022 |
serge-sans-paille <[email protected]> |
Cleanup codegen includes
This is a (fixed) recommit of https://reviews.llvm.org/D121169
after: 1061034926 before: 1063332844
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-in
Cleanup codegen includes
This is a (fixed) recommit of https://reviews.llvm.org/D121169
after: 1061034926 before: 1063332844
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121681
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Revision tags: llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3 |
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32977589 |
| 07-Mar-2022 |
Zi Xuan Wu <[email protected]> |
[CSKY] Enable TargetAsmStreamer/ELFStreamer and support asm directive of csky_attribute
Add support of parsing .csky_attribute directive and emit related target attributes in .csky.attribute section
[CSKY] Enable TargetAsmStreamer/ELFStreamer and support asm directive of csky_attribute
Add support of parsing .csky_attribute directive and emit related target attributes in .csky.attribute section. It does not emit attribute directive in assembly code, so only emit target attributes in ELF streamer. In ELF streamer, it handles the header EFlag and the csky_attribute section which contains some attribute items. The EFlag and attribute items are calculated from feature bits based on Subtarget.
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Revision tags: llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1 |
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a190fcdf |
| 07-Feb-2022 |
Zi Xuan Wu <[email protected]> |
[CSKY] Add inline asm constraints and related codegen support
There are kinds of inline asm constraints and corresponding register class or register as following.
'b': mGPRRegClass 'v': sGPRRegCl
[CSKY] Add inline asm constraints and related codegen support
There are kinds of inline asm constraints and corresponding register class or register as following.
'b': mGPRRegClass 'v': sGPRRegClass 'w': sFPR32RegClass or sFPR64RegClass 'c': C register 'z': R14 register 'h': HI register 'l': LO register 'y': HI or LO register
It also adds codegen test for inline-asm including constraints, clobbers and abi names.
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Revision tags: llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3 |
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82bb8a58 |
| 20-Jan-2022 |
Zi Xuan Wu <[email protected]> |
[CSKY] Add codegen support of GlobalTLSAddress lowering
There are static and dynamic TLS address lowering in DAG stage according to different TLS model. It needs PseudoTLSLA32 pseudo to get address
[CSKY] Add codegen support of GlobalTLSAddress lowering
There are static and dynamic TLS address lowering in DAG stage according to different TLS model. It needs PseudoTLSLA32 pseudo to get address of TLS-related entry which resides in constant pool.
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Revision tags: llvmorg-13.0.1-rc2 |
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065e0324 |
| 11-Jan-2022 |
Zi Xuan Wu <[email protected]> |
[CSKY] Add CSKYConstantIslands Pass to lift or duplicate constant pool entry
Loading constants inline is expensive on CSKY and it's in general better to place the constant nearby in code space and t
[CSKY] Add CSKYConstantIslands Pass to lift or duplicate constant pool entry
Loading constants inline is expensive on CSKY and it's in general better to place the constant nearby in code space and then it can be loaded with a simple 16/32 bit load instruction like lrw.
It needs lift or duplicates constant pool entry to make constant nearby so that lrw instruction can reach.
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8ddc8169 |
| 06-Jan-2022 |
Zi Xuan Wu <[email protected]> |
[CSKY] Lower leaf DAG node such as global symbol, frame address and jumptable, etc.
Lower global symbols such as call/external symbol. Lower other leaf DAG node such as frame address/block address/j
[CSKY] Lower leaf DAG node such as global symbol, frame address and jumptable, etc.
Lower global symbols such as call/external symbol. Lower other leaf DAG node such as frame address/block address/jumptable/vastart.
Normally some leaf symbols need reside in constant pool as ABI prefers, and are addressed by lrw or jsri instructions.
Every symbol in constant pool is lowered with one entry in target constant pool. The entry has different type corresponding to different leaf node such as blockaddress, jumptable, or global value.
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bdd7c53d |
| 06-Dec-2021 |
Zi Xuan Wu <[email protected]> |
[CSKY] Add compressed instruction mapping between 32-bit and 16-bit instruction
Add all CompressPat to map instructions between 16-bit and 32-bit with using the CompressInstEmitter infra. Although i
[CSKY] Add compressed instruction mapping between 32-bit and 16-bit instruction
Add all CompressPat to map instructions between 16-bit and 32-bit with using the CompressInstEmitter infra. Although it's only used in asm printer, also enable it in asm parser to debug mapping when -enable-csky-asm-compressed-inst is on.
Differential Revision: https://reviews.llvm.org/D115026
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Revision tags: llvmorg-13.0.1-rc1 |
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cf78715c |
| 01-Nov-2021 |
Zi Xuan Wu <[email protected]> |
[CSKY] First patch to construct codegen infra and generate first add instruction
Ooops. It constructs codegen infra and provide only basic code to generate first add instruction successfully.
Diffe
[CSKY] First patch to construct codegen infra and generate first add instruction
Ooops. It constructs codegen infra and provide only basic code to generate first add instruction successfully.
Differential Revision: https://reviews.llvm.org/D112206
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