[CodeGen] Split out the notions of MI invariance and MI dereferenceability.

Summary:
An IR load can be invariant, dereferenceable, neither, or both. But
currently, MI's notion of invariance is IR-i

[CodeGen] Split out the notions of MI invariance and MI dereferenceability.

Summary:
An IR load can be invariant, dereferenceable, neither, or both. But
currently, MI's notion of invariance is IR-invariant &&
IR-dereferenceable.

This patch splits up the notions of invariance and dereferenceability at
the MI level. It's NFC, so adds some probably-unnecessary
"is-dereferenceable" checks, which we can remove later if desired.

Reviewers: chandlerc, tstellarAMD

Subscribers: jholewinski, arsenm, nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D23371

llvm-svn: 281151

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[CodeGen] Rename MachineInstr::isInvariantLoad to isDereferenceableInvariantLoad. NFC

Summary:
I want to separate out the notions of invariance and dereferenceability
at the MI level, so that they

[CodeGen] Rename MachineInstr::isInvariantLoad to isDereferenceableInvariantLoad. NFC

Summary:
I want to separate out the notions of invariance and dereferenceability
at the MI level, so that they correspond to the equivalent concepts at
the IR level. (Currently an MI load is MI-invariant iff it's
IR-invariant and IR-dereferenceable.)

First step is renaming this function.

Reviewers: chandlerc

Subscribers: MatzeB, jfb, llvm-commits

Differential Revision: https://reviews.llvm.org/D23370

llvm-svn: 281125

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GlobalISel: move type information to MachineRegisterInfo.

We want each register to have a canonical type, which means the best place to
store this is in MachineRegisterInfo rather than on every Mach

GlobalISel: move type information to MachineRegisterInfo.

We want each register to have a canonical type, which means the best place to
store this is in MachineRegisterInfo rather than on every MachineInstr that
happens to use or define that register.

Most changes following from this are pretty simple (you need an MRI anyway if
you're going to be doing any transformations, so just check the type there).
But legalization doesn't really want to check redundant operands (when, for
example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's
operand type field to encode these constraints and limit legalization's work.

As an added bonus, more validation is possible, both in MachineVerifier and
MachineIRBuilder (coming soon).

llvm-svn: 281035

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Fix some more asserts after r279466.

That commit added a new version of Intrinsic::getName which should only
be called when the intrinsic has no overloaded types. There are several
debugging paths,

Fix some more asserts after r279466.

That commit added a new version of Intrinsic::getName which should only
be called when the intrinsic has no overloaded types. There are several
debugging paths, such as SDNode::dump which are printing the name of the
intrinsic but don't have the overloaded types. These paths should be ok
to just print the name instead of crashing.

The fix here is ultimately to just add a 'None' second argument as that
calls the overload capable getName, which is less efficient, but this is a
debugging path anyway, and not perf critical.

Thanks to Björn Pettersson for pointing out that there were more crashes.

llvm-svn: 279528

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Reset isUndef when removing subreg from a def operand

llvm-svn: 279437

GlobalISel: support irtranslation of icmp instructions.

llvm-svn: 278969

Use range algorithms instead of unpacking begin/end

No functionality change is intended.

llvm-svn: 278417

CodeGen: add new "intrinsic" MachineOperand kind.

This will be used during GlobalISel, where we need a more robust and readable
way to write tests than a simple immediate ID.

llvm-svn: 277209

MachineFunction: Return reference for getFrameInfo(); NFC

getFrameInfo() never returns nullptr so we should use a reference
instead of a pointer.

llvm-svn: 277017

[GlobalISel] Remove types on selected insts instead of using LLT().

LLT() has a particular meaning: it's one invalid type. But we really
want selected instructions to have no type whatsoever.

Also

[GlobalISel] Remove types on selected insts instead of using LLT().

LLT() has a particular meaning: it's one invalid type. But we really
want selected instructions to have no type whatsoever.

Also verify that types don't linger after ISel, and enable the verifier
on the AArch64 select test.

llvm-svn: 277001

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GlobalISel: allow multiple types on MachineInstrs.

llvm-svn: 276481

GlobalISel: implement low-level type with just size & vector lanes.

This should be all the low-level instruction selection needs to determine how
to implement an operation, with the remaining contex

GlobalISel: implement low-level type with just size & vector lanes.

This should be all the low-level instruction selection needs to determine how
to implement an operation, with the remaining context taken from the opcode
(e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math).

llvm-svn: 276158

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[inlineasm] Propagate operand constraints to the backend

When SelectionDAGISel transforms a node representing an inline asm
block, memory constraint information is not preserved. This can cause
cons

[inlineasm] Propagate operand constraints to the backend

When SelectionDAGISel transforms a node representing an inline asm
block, memory constraint information is not preserved. This can cause
constraints to be broken when a memory offset is of the form:

offset + frame index

when the frame is resolved.

By propagating the constraints all the way to the backend, targets can
enforce memory operands of inline assembly to conform to their constraints.

For MIPSR6, some instructions had their offsets reduced to 9 bits from
16 bits such as ll/sc. This becomes problematic when using inline assembly
to perform atomic operations, as an offset can generated that is too big to
encode in the instruction.

Reviewers: dsanders, vkalintris

Differential Review: https://reviews.llvm.org/D21615

llvm-svn: 275786

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[CodeGen] Refactor MachineMemOperand::Flags's target-specific flags.

Summary:
Make the target-specific flags in MachineMemOperand::Flags real, bona
fide enum values. This simplifies users, prevents

[CodeGen] Refactor MachineMemOperand::Flags's target-specific flags.

Summary:
Make the target-specific flags in MachineMemOperand::Flags real, bona
fide enum values. This simplifies users, prevents various constants
from going out of sync, and avoids the false sense of security provided
by declaring static members in classes and then forgetting to define
them inside of cpp files.

Reviewers: MatzeB

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D22372

llvm-svn: 275451

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[CodeGen] Refactor MachineMemOperand's Flags enum.

Summary:
- Give it a shorter name (because we're going to refer to it often from
SelectionDAG and friends).

- Split the flags and alignment into

[CodeGen] Refactor MachineMemOperand's Flags enum.

Summary:
- Give it a shorter name (because we're going to refer to it often from
SelectionDAG and friends).

- Split the flags and alignment into separate variables.

- Specialize FlagsEnumTraits for it, so we can do bitwise ops on it
without losing type information.

- Make some enum values constants in MachineMemOperand instead.
MOMaxBits should not be a valid Flag.

- Simplify some of the bitwise ops for dealing with Flags.

Reviewers: chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D22281

llvm-svn: 275438

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[MI] Clean up some loops over MachineInstr::memoperands(). NFC

Use range-based for loops and llvm::any_of instead of explicit
iterators.

llvm-svn: 275332

[MI] Fix MachineInstr::isInvariantLoad.

Summary:
Previously it would say we had an invariant load if any of the memory
operands were invariant. But the load should be invariant only if *all*
the me

[MI] Fix MachineInstr::isInvariantLoad.

Summary:
Previously it would say we had an invariant load if any of the memory
operands were invariant. But the load should be invariant only if *all*
the memory operands are invariant.

No testcase because this has proven to be very difficult to tickle in
practice. As just one example, ARM's ldrd instruction, which loads 64
bits into two 32-bit regs, is theoretically affected by this. But when
it's produced, it loses its memoperands' invariance bits!

Reviewers: jfb

Subscribers: llvm-commits, aemerson

Differential Revision: http://reviews.llvm.org/D22318

llvm-svn: 275331

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AMDGPU: Add convergent flag to INLINEASM instruction.

Differential Revision: http://reviews.llvm.org/D21214

llvm-svn: 273455

Pass DebugLoc and SDLoc by const ref.

This used to be free, copying and moving DebugLocs became expensive
after the metadata rewrite. Passing by reference eliminates a ton of
track/untrack operation

Pass DebugLoc and SDLoc by const ref.

This used to be free, copying and moving DebugLocs became expensive
after the metadata rewrite. Passing by reference eliminates a ton of
track/untrack operations. No functionality change intended.

llvm-svn: 272512

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Fix PR26655: Bail out if all regs of an inst BUNDLE have the correct kill flag

Summary:
While setting kill flags on instructions inside a BUNDLE, we bail out as soon
as we set kill flag on a registe

Fix PR26655: Bail out if all regs of an inst BUNDLE have the correct kill flag

Summary:
While setting kill flags on instructions inside a BUNDLE, we bail out as soon
as we set kill flag on a register. But we are missing a check when all the
registers already have the correct kill flag set. We need to bail out in that
case as well.

This patch refactors the old code and simply makes use of the addRegisterKilled
function in MachineInstr.cpp in order to determine whether to set/remove kill
on an instruction.

Reviewers: apazos, t.p.northover, pete, MatzeB

Subscribers: MatzeB, davide, llvm-commits

Differential Revision: http://reviews.llvm.org/D17356

llvm-svn: 269092

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AMDGPU/SI: add llvm.amdgcn.ps.live intrinsic

Summary:
This intrinsic returns true if the current thread belongs to a live pixel
and false if it belongs to a pixel that we are executing only for deri

AMDGPU/SI: add llvm.amdgcn.ps.live intrinsic

Summary:
This intrinsic returns true if the current thread belongs to a live pixel
and false if it belongs to a pixel that we are executing only for derivative
computation. It will be used by Mesa to implement gl_HelperInvocation.

Note that for pixels that are killed during the shader, this implementation
also returns true, but it doesn't matter because those pixels are always
disabled in the EXEC mask.

This unearthed a corner case in the instruction verifier, which complained
about a v_cndmask 0, 1, exec, exec<imp-use> instruction. That's stupid but
correct code, so make the verifier accept it as such.

Reviewers: arsenm, tstellarAMD

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D19191

llvm-svn: 267102

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Sink DI metadata usage out of MachineInstr.h and MachineInstrBuilder.h

MachineInstr.h and MachineInstrBuilder.h are very popular headers,
widely included across all LLVM backends. It turns out that

Sink DI metadata usage out of MachineInstr.h and MachineInstrBuilder.h

MachineInstr.h and MachineInstrBuilder.h are very popular headers,
widely included across all LLVM backends. It turns out that there only a
handful of TUs that actually care about DI operands on MachineInstrs.

After this change, touching DebugInfoMetadata.h and rebuilding llc only
needs 112 actions instead of 542.

llvm-svn: 266351

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[MachineInstr] Teach the print method about RegisterBank.

Properly print either the register class or the register bank or a
virtual register.
Get rid of a few ifdefs in the process.

llvm-svn: 2657

[MachineInstr] Teach the print method about RegisterBank.

Properly print either the register class or the register bank or a
virtual register.
Get rid of a few ifdefs in the process.

llvm-svn: 265745

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Revert "NFC: static_assert instead of comment"

This reverts commit fa36fcff16c7d4f78204d6296bf96c3558a4a672.

Causes the following Windows failure:

C:\Buildbot\Slave\llvm-clang-lld-x86_64-scei-ps

Revert "NFC: static_assert instead of comment"

This reverts commit fa36fcff16c7d4f78204d6296bf96c3558a4a672.

Causes the following Windows failure:

C:\Buildbot\Slave\llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast\llvm.src\lib\CodeGen\MachineInstr.cpp(762):
error C2338: must be trivially copyable to memmove

llvm-svn: 264516

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NFC: static_assert instead of comment

Summary: isPodLike is as close as we have for is_trivially_copyable.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D18483

llvm-svn

NFC: static_assert instead of comment

Summary: isPodLike is as close as we have for is_trivially_copyable.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D18483

llvm-svn: 264515

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