| 57b5369f | 07-Feb-2025 |
Sandie Cao <[email protected]> |
riscv: dts: starfive: fml13v01: enable pcie1
Starfive Soc common defines GPIO28 as pcie1 reset, GPIO21 as pcie1 wakeup; But the FML13V01 board uses GPIO21 as pcie1 reset, GPIO28 as pcie1 wakeup; red
riscv: dts: starfive: fml13v01: enable pcie1
Starfive Soc common defines GPIO28 as pcie1 reset, GPIO21 as pcie1 wakeup; But the FML13V01 board uses GPIO21 as pcie1 reset, GPIO28 as pcie1 wakeup; redefine pcie1 gpio and enable pcie1 for pcie based Wi-Fi.
Signed-off-by: Sandie Cao <[email protected]> Tested-by: Maud Spierings <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
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| 4bdea6e3 | 13-Feb-2025 |
Conor Dooley <[email protected]> |
riscv: dts: starfive: remove non-existent dac from jh7110
The jh7110 boards do not have a Rohm DAC on them as far as I can tell, and they certainly do not have a dh2228fv, as this device does not ac
riscv: dts: starfive: remove non-existent dac from jh7110
The jh7110 boards do not have a Rohm DAC on them as far as I can tell, and they certainly do not have a dh2228fv, as this device does not actually exist! Remove the dac nodes from the devicetrees as it is not acceptable to pretend to have a device on a board in order to bind the spidev driver in Linux.
Signed-off-by: Conor Dooley <[email protected]>
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| c8b72c30 | 28-Oct-2024 |
Sandie Cao <[email protected]> |
riscv: dts: starfive: add DeepComputing FML13V01 board device tree
The FML13V01 board from DeepComputing incorporates a StarFive JH7110 SoC. It is a mainboard designed for the Framework Laptop 13 Ch
riscv: dts: starfive: add DeepComputing FML13V01 board device tree
The FML13V01 board from DeepComputing incorporates a StarFive JH7110 SoC. It is a mainboard designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.
The FML13V01 board features: - StarFive JH7110 SoC - LPDDR4 8GB - eMMC 32GB or 128GB - QSPI Flash - MicroSD Slot - PCIe-based Wi-Fi - 4 USB-C Ports - Port 1: PD 3.0 (60W Max), USB 3.2 Gen 1, DP 1.4 (4K@30Hz/2.5K@60Hz) - Port 2: PD 3.0 (60W Max), USB 3.2 Gen 1 - Port 3 & 4: USB 3.2 Gen 1
Create the DTS file for the DeepComputing FML13V01 board. Based on 'jh7110-common.dtsi', usb0 is enabled and is set to operate as a "host".
Signed-off-by: Sandie Cao <[email protected]> [[email protected]: revised the description, updated some nodes] Signed-off-by: Alex Elder <[email protected]> Signed-off-by: Guodong Xu <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
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| 817eac16 | 28-Oct-2024 |
Guodong Xu <[email protected]> |
riscv: dts: starfive: jh7110-common: move usb0 config to board dts
The JH7110 USB0 can operate as a dual-role USB device. Different boards can have different configuration.
For all current boards
riscv: dts: starfive: jh7110-common: move usb0 config to board dts
The JH7110 USB0 can operate as a dual-role USB device. Different boards can have different configuration.
For all current boards this device operates in peripheral mode, but on a new board this operates in host mode. This property will no longer be common, so define the "dr_mode" property in the board files rather than in the common DTSI file.
Signed-off-by: Alex Elder <[email protected]> Signed-off-by: Guodong Xu <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
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| 825bb692 | 22-Oct-2024 |
E Shattow <[email protected]> |
riscv: dts: starfive: Update ethernet phy0 delay parameter values for Star64
Improve function of Star64 bottom network port phy0 with updated delay values. Initial upstream patches supporting Star64
riscv: dts: starfive: Update ethernet phy0 delay parameter values for Star64
Improve function of Star64 bottom network port phy0 with updated delay values. Initial upstream patches supporting Star64 use the same vendor board support package parameters known to result in an unreliable bottom network port.
Success acquiring DHCP lease and no dropped packets to ping LAN address: rx 900: tx 1500 1650 1800 1950 rx 750: tx 1650 1800 1950 rx 600: tx 1800 1950 rx 1050: tx 1650 1800 1950 rx 1200: tx 1500 1650 1800 1950 rx 1350: tx 1500 1650 1800 1950 rx 1500: tx 1500 1650 1800 1950 rx 1650: tx 1500 1650 1800 1950 rx 1800: tx 1500 1650 1800 1950 rx 1900: tx 1950 rx 1950: tx 1950
Failure acquiring DHCP lease or many dropped packets: rx 450: tx 1500 1800 1950 rx 600: tx 1200 1350 1650 rx 750: tx 1350 1500 rx 900: tx 1200 1350 rx 1050: tx 1050 1200 1350 1500 rx 1200: tx 1350 rx 1350: tx 1350 rx 1500: tx 1200 1350 rx 1650: tx 1050 1200 1350 rx 1800: tx 1050 1200 1350 rx 1900: tx 1500 1650 1800 rx 1950: tx 1200 1350
Non-functional: rx 0: tx 0 150 300 450 600 750 900 1050 1200 1350 1500 1650 1800 1950 rx 150: tx 0 150 300 450 600 750 900 1050 1200 1350 1500 1650 1800 1950 rx 300: tx 0 150 300 450 600 750 900 1050 1200 1350 1500 1650 1800 1950 rx 450: tx 0 150 300 450 600 750 900 1050 1200 1350 1650 rx 600: tx 0 150 300 450 600 750 900 1050 rx 750: tx 0 150 300 450 600 750 900 1050 1200 rx 900: tx 0 150 300 450 600 750 900 1050 rx 1050: tx 0 150 300 450 600 750 900 rx 1200: tx 0 150 300 450 600 750 900 1050 1200 rx 1350: tx 0 150 300 450 600 750 900 1050 1200 rx 1500: tx 0 150 300 450 600 750 900 1050 rx 1650: tx 0 150 300 450 600 750 900 rx 1800: tx 0 150 300 450 600 750 900 rx 1900: tx 0 150 300 450 600 750 900 1050 1200 1350 rx 1950: tx 0 150 300 450 600 750 900 1050
Selecting the median of all working rx delay values 1500 combined with tx delay values 1500, 1650, 1800, and 1950 only the tx delay value of 1950 (default) is reliable as tested in both Linux 6.11.2 and U-Boot v2024.10
Signed-off-by: E Shattow <[email protected]> CC: [email protected] Fixes: 2606bf583b962 ("riscv: dts: starfive: add Star64 board devicetree") Acked-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
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| edbce932 | 03-Jun-2024 |
Matthias Brugger <[email protected]> |
riscv: dts: starfive: Update flash partition layout
Up to now, the describe flash partition layout has some gaps. Use the whole flash chip by getting rid of the gaps.
Suggested-by: Heinrich Schucha
riscv: dts: starfive: Update flash partition layout
Up to now, the describe flash partition layout has some gaps. Use the whole flash chip by getting rid of the gaps.
Suggested-by: Heinrich Schuchardt <[email protected]> Signed-off-by: Matthias Brugger <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Reviewed-by: Heinrich Schuchardt <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
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| 9276badd | 29-Apr-2024 |
Jisheng Zhang <[email protected]> |
riscv: dts: starfive: add Milkv Mars board device tree
The Milkv Mars is a development board based on the Starfive JH7110 SoC. The board features:
- JH7110 SoC - 1/2/4/8 GiB LPDDR4 DRAM - AXP15060
riscv: dts: starfive: add Milkv Mars board device tree
The Milkv Mars is a development board based on the Starfive JH7110 SoC. The board features:
- JH7110 SoC - 1/2/4/8 GiB LPDDR4 DRAM - AXP15060 PMIC - 40 pin GPIO header - 3x USB 3.0 host port - 1x USB 2.0 host port - 1x M.2 E-Key - 1x eMMC slot - 1x MicroSD slot - 1x QSPI Flash - 1x 1Gbps Ethernet port - 1x HDMI port - 1x 2-lane DSI and 1x 4-lane DSI - 1x 2-lane CSI
Add the devicetree file describing the currently supported features, namely PMIC, UART, I2C, GPIO, SD card, QSPI Flash, eMMC and Ethernet.
Signed-off-by: Jisheng Zhang <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
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| 07da6ddf | 29-Apr-2024 |
Jisheng Zhang <[email protected]> |
riscv: dts: starfive: visionfive 2: add "disable-wp" for tfcard
No physical write-protect line is present, so setting "disable-wp".
Signed-off-by: Jisheng Zhang <[email protected]> Reviewed-by: Em
riscv: dts: starfive: visionfive 2: add "disable-wp" for tfcard
No physical write-protect line is present, so setting "disable-wp".
Signed-off-by: Jisheng Zhang <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
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| 0ffce9d4 | 29-Apr-2024 |
Jisheng Zhang <[email protected]> |
riscv: dts: starfive: visionfive 2: add tf cd-gpios
Per VisionFive 2 1.2B, and 1.3A boards' SCH, GPIO 41 is used as card detect. So add "cd-gpios" property for this.
Signed-off-by: Jisheng Zhang <j
riscv: dts: starfive: visionfive 2: add tf cd-gpios
Per VisionFive 2 1.2B, and 1.3A boards' SCH, GPIO 41 is used as card detect. So add "cd-gpios" property for this.
Signed-off-by: Jisheng Zhang <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
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