| 48e7821b | 07-Feb-2025 |
Tudor Ambarus <[email protected]> |
arm64: dts: exynos: gs101: add SRAM node
SRAM is used by the ACPM protocol to retrieve the ACPM channels
information, which includes the TX/RX rings among other channel
configuration data. Add the S
arm64: dts: exynos: gs101: add SRAM node
SRAM is used by the ACPM protocol to retrieve the ACPM channels
information, which includes the TX/RX rings among other channel
configuration data. Add the SRAM node.
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[krzysztof: correct alphabetical node placement]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| ae32b65c | 10-Feb-2025 |
André Draszik <[email protected]> |
arm64: dts: exynos: gs101: add reboot-mode support (SYSIP_DAT0)
syscon-reboot-mode can be used to indicate the reboot mode for the
bootloader.
While not sufficient for all boot modes, the boot load
arm64: dts: exynos: gs101: add reboot-mode support (SYSIP_DAT0)
syscon-reboot-mode can be used to indicate the reboot mode for the
bootloader.
While not sufficient for all boot modes, the boot loader does use
SYSIP_DAT0 (PMU + 0x0810) to determine some of the actions it should
take. This change helps it deciding what to do in those cases.
For complete support, we'll also have to write the boot mode to an
NVMEM storage location, but we have no upstream driver for that yet.
Nevertheless, this patch is a step towards full support for the boot
mode.
Note1: Android also uses 'shutdown,thermal' and
shutdown,thermal,battery', but that can not be described in DT as ','
is used to denote vendor prefixes. I've left them out from here for
that reason.
Note2: downstream / bootloader recognizes one more mode: 'dm-verity
device corrupted' with value 0x50, but we can not describe that in DT
using a property name due to the space, so it's been left out from here
as well. This string appears to come from drivers/md/dm-verity-target.c
and should probably be changed there in a follow-up patch, so that it
can be used in reboot-mode nodes like this one here.
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| 6572a93a | 10-Feb-2025 |
André Draszik <[email protected]> |
arm64: dts: exynos: gs101: align poweroff writes with downstream
For power off, downstream only clears bit 8 and leaves all other bits
untouched, whereas this here ends up setting bit 8 and clearing
arm64: dts: exynos: gs101: align poweroff writes with downstream
For power off, downstream only clears bit 8 and leaves all other bits
untouched, whereas this here ends up setting bit 8 and clearing all
others, due to how sysconf-poweroff parses the DT.
I noticed this discrepancy while debugging some reboot related
differences between up- and downstream and it's useful to align the
behaviour here.
Note: for reboot downstream seems to be incorrectly writing 0x00000002
and not just setting bit 1 (which is the only R/W bit in this
register), so we keep that one as-is here.
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| 825c4bfd | 17-Jan-2025 |
André Draszik <[email protected]> |
arm64: dts: exynos: gs101-raven: add new board file
Raven is Google's code name for Pixel 6 Pro. Similar to Pixel 6
(Oriole), this is also based around its Tensor gs101 SoC.
For now, the relevant d
arm64: dts: exynos: gs101-raven: add new board file
Raven is Google's code name for Pixel 6 Pro. Similar to Pixel 6
(Oriole), this is also based around its Tensor gs101 SoC.
For now, the relevant difference here is the display resolution:
1440 x 3120 instead of 1080 x 2400.
Create a new board file to reflect this difference.
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| 58dbafb7 | 17-Jan-2025 |
André Draszik <[email protected]> |
arm64: dts: exynos: gs101-oriole: move common Pixel6 & 6Pro parts into a .dtsi
In order to support Pixel 6 (Oriole), Pixel 6 Pro (Raven), Pixel 6a
(Bluejay), and all other versions correctly, we hav
arm64: dts: exynos: gs101-oriole: move common Pixel6 & 6Pro parts into a .dtsi
In order to support Pixel 6 (Oriole), Pixel 6 Pro (Raven), Pixel 6a
(Bluejay), and all other versions correctly, we have to be able to
distinguish them properly as we add support for more features.
For example, Raven has a larger display. There are other differences,
like battery design capacity, etc.
Move all the parts that are common for now into a
gs101-pixel-common.dtsi, and just leave the display related things in
gs101-oriole.dts.
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| befbb62c | 17-Jan-2025 |
André Draszik <[email protected]> |
arm64: dts: exynos: gs101-oriole: configure simple-framebuffer
The bootloader configures the display hardware for a framebuffer at the
given address, let's add a simple-framebuffer node here until w
arm64: dts: exynos: gs101-oriole: configure simple-framebuffer
The bootloader configures the display hardware for a framebuffer at the
given address, let's add a simple-framebuffer node here until we get a
proper DRM driver.
This has several benefits since it's an OLED display:
* energy consumption goes down significantly, as it changes from white
(as left by bootloader) to black (linux console), and we generally
don't run out of battery anymore when plugged into a USB port
* less of a burn-in effect I assume
* phone stays cooler due to reduced energy consumption by display
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| 817473b6 | 03-Dec-2024 |
André Draszik <[email protected]> |
arm64: dts: exynos: gs101-oriole: add pd-disable and typec-power-opmode
When the serial console is enabled, we need to disable power delivery
since serial uses the SBU1/2 pins and appears to confuse
arm64: dts: exynos: gs101-oriole: add pd-disable and typec-power-opmode
When the serial console is enabled, we need to disable power delivery
since serial uses the SBU1/2 pins and appears to confuse the TCPCI,
resulting in endless interrupts.
For now, change the DT such that the serial console continues working.
Note1: We can not have both typec-power-opmode and
new-source-frs-typec-current active at the same time, as otherwise DT
binding checks complain.
Note2: When using a downstream DT, the Pixel boot-loader will modify
the DT accordingly before boot, but for this upstream DT it doesn't
know where to find the TCPCI node. The intention is for this commit to
be reverted once an updated Pixel boot-loader becomes available.
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-5-1412783a6b01@linaro.org
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| ddbf40d8 | 03-Dec-2024 |
André Draszik <[email protected]> |
arm64: dts: exynos: gs101-oriole: enable Maxim max77759 TCPCi
On Pixel 6 (and Pro), a max77759 companion PMIC for USB Type-C
applications is used, which contains four functional blocks (at
distinct
arm64: dts: exynos: gs101-oriole: enable Maxim max77759 TCPCi
On Pixel 6 (and Pro), a max77759 companion PMIC for USB Type-C
applications is used, which contains four functional blocks (at
distinct I2C addresses):
* top (including GPIO)
* charger
* fuel gauge
* TCPCi
While in the same package, TCPCi and Fuel Gauge have separate I2C
addresses, interrupt lines and interrupt status registers and can be
treated independently.
The TCPCi is required to detect and handle connector orientation in
Pixel's USB PHY driver, and to configure the USB controller's role
(host vs device).
This change adds the TCPCi part as it can be independent and doesn't
need a top-level MFD.
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Tested-by: Peter Griffin <[email protected]>
Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-4-1412783a6b01@linaro.org
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| 95350c0e | 03-Dec-2024 |
André Draszik <[email protected]> |
arm64: dts: exynos: gs101: allow stable USB phy Vbus detection
For the DWC3 core to reliably detect the connected phy's Vbus state, we
need to disable phy suspend.
Add
snps,dis_u2_susphy_quirk
arm64: dts: exynos: gs101: allow stable USB phy Vbus detection
For the DWC3 core to reliably detect the connected phy's Vbus state, we
need to disable phy suspend.
Add
snps,dis_u2_susphy_quirk
snps,dis_u3_susphy_quirk
to do that.
While at it, also add
snps,has-lpm-erratum
as this is set downstream which implies that the core was configured
with LPM Erratum. We should do the same here.
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Tested-by: Peter Griffin <[email protected]>
Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-3-1412783a6b01@linaro.org
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| 2510bca4 | 18-Jun-2024 |
André Draszik <[email protected]> |
arm64: dts: exynos: gs101-oriole: add placeholder regulators for USB phy
The USB phy requires various power supplies to work.
While we don't have a PMIC driver yet, the supplies should still be
add
arm64: dts: exynos: gs101-oriole: add placeholder regulators for USB phy
The USB phy requires various power supplies to work.
While we don't have a PMIC driver yet, the supplies should still be
added to the DT.
Add some placeholders, which will be replaced with the real ones once
we implement PMIC.
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| 4db286b0 | 30-Apr-2024 |
André Draszik <[email protected]> |
arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl
The pinctrl instances hsi1, gsactrl, and gsacore need a clock for
register access to work.
Since we haven't implemented the rel
arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl
The pinctrl instances hsi1, gsactrl, and gsacore need a clock for
register access to work.
Since we haven't implemented the relevant CMUs for the clocks required
by these instances just add empty clocks for now so as to make the DT
pass the validation checks.
Once the clocks are implmented in the gs101 clock driver, these should
be updated then.
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-4-14fc988139dd@linaro.org
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| aaafb21e | 30-Apr-2024 |
Peter Griffin <[email protected]> |
arm64: dts: exynos: gs101: enable ufs, phy on oriole & define ufs regulator
Enable ufs & ufs phy nodes for Oriole. Also define the ufs regulator node.
ufs regulator is a stub until full s2mpg11 sla
arm64: dts: exynos: gs101: enable ufs, phy on oriole & define ufs regulator
Enable ufs & ufs phy nodes for Oriole. Also define the ufs regulator node.
ufs regulator is a stub until full s2mpg11 slave pmic support is added.
The gpio defined is for the BOOTLD0 (gs101) signal connected to
UFS_EN(s2mpg11) gpio enabled voltage rail for UFS.
Signed-off-by: Peter Griffin <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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