clk: tegra: Add stubs needed for compile testing

These stubs are needed to allow the tegra-cpuidle driver to be
compile-tested.

Signed-off-by: Thierry Reding <[email protected]>

clk: tegra: Add stubs needed for compile-testing

Add stubs needed for compile-testing of Tegra memory drivers.

Signed-off-by: Dmitry Osipenko <[email protected]>
Signed-off-by: Thierry Reding <tredi

clk: tegra: Add stubs needed for compile-testing

Add stubs needed for compile-testing of Tegra memory drivers.

Signed-off-by: Dmitry Osipenko <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

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clk: tegra: Add PLLE HW power sequencer control

PLLE has a hardware power sequencer logic which is a state machine
that can power on/off PLLE without any software intervention. The
sequencer has two

clk: tegra: Add PLLE HW power sequencer control

PLLE has a hardware power sequencer logic which is a state machine
that can power on/off PLLE without any software intervention. The
sequencer has two inputs, one from XUSB UPHY PLL and the other from
SATA UPHY PLL. PLLE provides reference clock to XUSB and SATA UPHY
PLLs. When both of the downstream PLLs are powered-off, PLLE hardware
power sequencer will automatically power off PLLE for power saving.

XUSB and SATA UPHY PLLs also have their own hardware power sequencer
logic. XUSB UPHY PLL is shared between XUSB SuperSpeed ports and PCIE
controllers. The XUSB UPHY PLL hardware power sequencer has inputs
from XUSB and PCIE. When all of the XUSB SuperSpeed ports and PCIE
controllers are in low power state, XUSB UPHY PLL hardware power
sequencer automatically power off PLL and flags idle to PLLE hardware
power sequencer. Similar applies to SATA UPHY PLL.

PLLE hardware power sequencer has to be enabled after both downstream
sequencers are enabled.

This commit adds two helper functions:
1. tegra210_plle_hw_sequence_start() for XUSB PADCTL driver to enable
PLLE hardware sequencer at proper time.

2. tegra210_plle_hw_sequence_is_enabled() for XUSB PADCTL driver to
check whether PLLE hardware sequencer has been enabled or not.

Signed-off-by: JC Kuo <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

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memory: tegra124-emc: Make driver modular

Add modularization support to the Tegra124 EMC driver, which now can be
compiled as a loadable kernel module.

Note that EMC clock must be registered at clk

memory: tegra124-emc: Make driver modular

Add modularization support to the Tegra124 EMC driver, which now can be
compiled as a loadable kernel module.

Note that EMC clock must be registered at clk-init time, otherwise PLLM
will be disabled as unused clock at boot time if EMC driver is compiled
as a module. Hence add a prepare/complete callbacks. similarly to what is
done for the Tegra20/30 EMC drivers.

Tested-by: Nicolas Chauvet <[email protected]>
Signed-off-by: Dmitry Osipenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>

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clk: tegra: Implement Tegra210 EMC clock

The EMC clock needs to carefully coordinate with the EMC controller
programming to make sure external memory can be properly clocked. Do so
by hooking up the

clk: tegra: Implement Tegra210 EMC clock

The EMC clock needs to carefully coordinate with the EMC controller
programming to make sure external memory can be properly clocked. Do so
by hooking up the EMC clock with an EMC provider that will specify which
rates are supported by the EMC and provide a callback to use for setting
the clock rate at the EMC.

Based on work by Peter De Schrijver <[email protected]>.

Signed-off-by: Joseph Lo <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

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clk: tegra: Export functions for EMC clock scaling

Export functions to allow accessing the CAR register required by EMC
clock scaling. These functions will be used to access the CAR register
as part

clk: tegra: Export functions for EMC clock scaling

Export functions to allow accessing the CAR register required by EMC
clock scaling. These functions will be used to access the CAR register
as part of the scaling sequence.

Signed-off-by: Joseph Lo <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

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clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP

The new CPUIDLE driver uses the Tegra's CLK API and that driver won't
strictly depend on CONFIG_PM_SLEEP, hence add the required stubs

clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP

The new CPUIDLE driver uses the Tegra's CLK API and that driver won't
strictly depend on CONFIG_PM_SLEEP, hence add the required stubs in
order to allow compiling of the new driver with the CONFIG_PM_SLEEP=n.

Signed-off-by: Dmitry Osipenko <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

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clk: tegra: Add Tegra20/30 EMC clock implementation

A proper External Memory Controller clock rounding and parent selection
functionality is required by the EMC drivers, it is not available using
th

clk: tegra: Add Tegra20/30 EMC clock implementation

A proper External Memory Controller clock rounding and parent selection
functionality is required by the EMC drivers, it is not available using
the generic clock implementation because only the Memory Controller driver
is aware of what clock rates are actually available for a particular
device. EMC drivers will have to register a Tegra-specific CLK-API
callback which will perform rounding of a requested rate. EMC clock users
won't be able to request EMC clock by getting -EPROBE_DEFER until EMC
driver is probed and the callback is set up.

The functionality is somewhat similar to the clk-emc.c which serves
Tegra124+ SoCs. The later HW generations support more parent clock sources
and the HW configuration / integration with the EMC drivers differs a tad
from the older gens, hence it's not really worth to try to squash
everything into a single source file.

Acked-by: Peter De Schrijver <[email protected]>
Signed-off-by: Dmitry Osipenko <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms and c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms and conditions of the gnu general public license
version 2 as published by the free software foundation this program
is distributed in the hope it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details you should have received a copy of the gnu general
public license along with this program if not see http www gnu org
licenses

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 228 file(s).

Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Allison Randal <[email protected]>
Reviewed-by: Steve Winslow <[email protected]>
Reviewed-by: Richard Fontana <[email protected]>
Reviewed-by: Alexios Zavras <[email protected]>
Cc: [email protected]
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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clk: tegra: MBIST work around for Tegra210

Tegra210 has a hw bug which can cause IP blocks to lock up when ungating a
domain. The reason is that the logic responsible for resetting the memory
built-

clk: tegra: MBIST work around for Tegra210

Tegra210 has a hw bug which can cause IP blocks to lock up when ungating a
domain. The reason is that the logic responsible for resetting the memory
built-in self test mode can come up in an undefined state because its
clock is gated by a second level clock gate (SLCG). Work around this by
making sure the logic will get some clock edges by ensuring the relevant
clock is enabled and temporarily override the relevant SLCGs.
Unfortunately for some IP blocks, the control bits for overriding the
SLCGs are not in CAR, but in the IP block itself. This means we need to
map a few extra register banks in the clock code.

Signed-off-by: Peter De Schrijver <[email protected]>
Reviewed-by: Jon Hunter <[email protected]>
Tested-by: Jon Hunter <[email protected]>
Tested-by: Hector Martin <[email protected]>
Tested-by: Andre Heider <[email protected]>
Tested-by: Mikko Perttunen <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

fixup mbist

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clk: tegra: Add SATA seq input control

This will be used by the powergating driver to ensure proper sequencer
state when the SATA domain is powergated.

Signed-off-by: Peter De Schrijver <pdeschrijv

clk: tegra: Add SATA seq input control

This will be used by the powergating driver to ensure proper sequencer
state when the SATA domain is powergated.

Signed-off-by: Peter De Schrijver <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

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clk: tegra: Handle UTMIPLL IDDQ

Export UTMIPLL IDDQ functions. These will be needed when powergating the
XUSB partition.

Signed-off-by: BH Hsieh <[email protected]>
Signed-off-by: Peter De Schrijve

clk: tegra: Handle UTMIPLL IDDQ

Export UTMIPLL IDDQ functions. These will be needed when powergating the
XUSB partition.

Signed-off-by: BH Hsieh <[email protected]>
Signed-off-by: Peter De Schrijver <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

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clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs

On Tegra210, hardware control of the SATA and XUSB pad PLLs must be
done during the UPHY enable sequence rather than the PLLE e

clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs

On Tegra210, hardware control of the SATA and XUSB pad PLLs must be
done during the UPHY enable sequence rather than the PLLE enable
sequence. Export functions to do this so that hardware control can
be enabled from the XUSB padctl driver.

Signed-off-by: Andrew Bresticker <[email protected]>
Signed-off-by: Rhyland Klein <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

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clk: tegra: Properly include clk.h

Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are using
it. Also add in a clkdev.h inclu

clk: tegra: Properly include clk.h

Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are using
it. Also add in a clkdev.h include that was missing in a file
using clkdev APIs.

Cc: Peter De Schrijver <[email protected]>
Cc: Thierry Reding <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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clk: tegra: make tegra_clocks_apply_init_table() arch_initcall

tegra_clocks_apply_init_table() needs to be called after the udelay
loop has been calibrated (see commit
441f199a37cfd66c5dd8dd45490bd3

clk: tegra: make tegra_clocks_apply_init_table() arch_initcall

tegra_clocks_apply_init_table() needs to be called after the udelay
loop has been calibrated (see commit
441f199a37cfd66c5dd8dd45490bd3ea6971117d ("clk: tegra: defer
application of init table") for why that is). On existing Tegra SoCs
this was done by calling tegra_clocks_apply_init_table() from
tegra_dt_init(). To make this also work on ARM64, we need to change
this into an initcall. tegra_dt_init() is called from
customize_machine which is an arch_initcall. Therefore this should
also work on existing 32bit Tegra SoCs.

Tested on Tegra20 (ventana), Tegra30 (beaverboard), Tegra124 (jetson TK1) and
Tegra132.

Signed-off-by: Peter De Schrijver <[email protected]>
[[email protected]: tweaked the commit message]
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Prashant Gaikwad <[email protected]>
Cc: Mike Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Alexandre Courbot <[email protected]>

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clk: tegra: remove legacy reset APIs

Now that no code uses the custom Tegra module reset API, we can remove
its implementation.

Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Thier

clk: tegra: remove legacy reset APIs

Now that no code uses the custom Tegra module reset API, we can remove
its implementation.

Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
Acked-By: Peter De Schrijver <[email protected]>

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clk: tegra: fix ifdef for tegra_periph_reset_assert inline

Commit 7064f6b "clk: tegra: provide tegra_periph_reset_assert
alternative" added ifdef'd static inline versions of some functions,
but test

clk: tegra: fix ifdef for tegra_periph_reset_assert inline

Commit 7064f6b "clk: tegra: provide tegra_periph_reset_assert
alternative" added ifdef'd static inline versions of some functions,
but tested ARCH_TEGRA rather than CONFIG_ARCH_TEGRA, thus disabling
these function in all cases. In some cases, this caused HW modules to
misbehave; for example, the Tegra I2C driver BUG()d during boot on
Seaboard.

Reported-by: Olof Johansson <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
Tested-by: Paul Walmsley <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>

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clk: tegra: provide tegra_periph_reset_assert alternative

We have some tegra device drivers that are written to be platform
independent but still use the tegra specific tegra_periph_reset_assert
fun

clk: tegra: provide tegra_periph_reset_assert alternative

We have some tegra device drivers that are written to be platform
independent but still use the tegra specific tegra_periph_reset_assert
function. In order to build and link them without errors,
this provides a static inline version of these functions that
does nothing when Tegra support is disabled.

Signed-off-by: Arnd Bergmann <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>
[[email protected]: fixed up trivial merge issue]

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clk: tegra: Use common of_clk_init function

Use common of_clk_init() function for clocks initialization.

Signed-off-by: Prashant Gaikwad <[email protected]>
Reviewed-by: Thierry Reding <thierry.r

clk: tegra: Use common of_clk_init function

Use common of_clk_init() function for clocks initialization.

Signed-off-by: Prashant Gaikwad <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>

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clk: tegra: defer application of init table

The Tegra clock driver is initialized during the ARM machine descriptor's
.init_irq() hook. It can't be initialized earlier, since dynamic memory
usage is

clk: tegra: defer application of init table

The Tegra clock driver is initialized during the ARM machine descriptor's
.init_irq() hook. It can't be initialized earlier, since dynamic memory
usage is required. It can't be initialized later, since the .init_timer()
hook needs the clocks initialized. However, at this time, udelay()
doesn't work.

The Tegra clock initialization table may enable some PLLs. Enabling a PLL
may require usage of udelay(). Hence, this can't happen right when the
clock driver is initialized.

To solve this, separate the clock driver initialization from the clock
table processing, so they can execute at separate times.

Signed-off-by: Stephen Warren <[email protected]>

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ARM: tegra: remove legacy clock code

Remove all legacy clock code from mach-tegra.

Signed-off-by: Prashant Gaikwad <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>

ARM: tegra: migrate to new clock code

Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peri

ARM: tegra: migrate to new clock code

Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h

Signed-off-by: Prashant Gaikwad <[email protected]>
[swarren: use to_clk_periph_gate().]
Signed-off-by: Stephen Warren <[email protected]>

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ARM: tegra: move tegra_cpu_car.h to linux/clk/tegra.h

tegra_cpu_car_ops struct is going to be accessed from drivers/clk/tegra.
Move the tegra_cpu_car_ops to include/linux/clk/tegra.h.

Signed-off-by

ARM: tegra: move tegra_cpu_car.h to linux/clk/tegra.h

tegra_cpu_car_ops struct is going to be accessed from drivers/clk/tegra.
Move the tegra_cpu_car_ops to include/linux/clk/tegra.h.

Signed-off-by: Prashant Gaikwad <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>

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