clk: at91: fix the build with binutils 2.27

There is an issue when build with older versions of binutils 2.27.0,

arch/arm/mach-at91/pm_suspend.S: Assembler messages:
arch/arm/mach-at91/pm_suspend.S

clk: at91: fix the build with binutils 2.27

There is an issue when build with older versions of binutils 2.27.0,

arch/arm/mach-at91/pm_suspend.S: Assembler messages:
arch/arm/mach-at91/pm_suspend.S:1086: Error: garbage following instruction -- `ldr tmp1,=0x00020010UL'

Use UL() macro to fix the issue in assembly file.

Fixes: 4fd36e458392 ("ARM: at91: pm: add plla disable/enable support for sam9x60")
Signed-off-by: Kefeng Wang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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ARM: at91: PM: add cpu idle support for sama7g5

Add CPU idle support for SAMA7G5. Support will make use of PMC_CPU_RATIO
register to divide the CPU clock by 16 before switching it to idle and
use au

ARM: at91: PM: add cpu idle support for sama7g5

Add CPU idle support for SAMA7G5. Support will make use of PMC_CPU_RATIO
register to divide the CPU clock by 16 before switching it to idle and
use automatic self-refresh option of DDR controller.

Signed-off-by: Claudiu Beznea <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clk: at91: add register definition for sama7g5's master clock

Add register definitions for SAMA7G5's master clock. These would be
also used by architecture specific power saving code.

Signed-off-by

clk: at91: add register definition for sama7g5's master clock

Add register definitions for SAMA7G5's master clock. These would be
also used by architecture specific power saving code.

Signed-off-by: Claudiu Beznea <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clk: at91: clk-utmi: add utmi support for sama7g5

Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on b

clk: at91: clk-utmi: add utmi support for sama7g5

Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on board crystal oscillator frequency.

Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: at91: add macro for pll ids mask

Add macro for PLL IDs mask.

Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/1595403506-8209-16-git-send-email-clau

clk: at91: add macro for pll ids mask

Add macro for PLL IDs mask.

Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: at91: clk-master: add master clock support for SAMA7G5

Add master clock support (MCK1..4) for SAMA7G5. SAMA7G5's PMC has
multiple master clocks feeding different subsystems. One of them
feeds i

clk: at91: clk-master: add master clock support for SAMA7G5

Add master clock support (MCK1..4) for SAMA7G5. SAMA7G5's PMC has
multiple master clocks feeding different subsystems. One of them
feeds image subsystem and is changeable based on image subsystem
needs.

Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: at91: move sam9x60's PLL register offsets to PMC header

Move SAM9X60's PLL register offsets to PMC header so that the
definitions would also be available from arch/arm/mach-at91/pm_suspend.S.
T

clk: at91: move sam9x60's PLL register offsets to PMC header

Move SAM9X60's PLL register offsets to PMC header so that the
definitions would also be available from arch/arm/mach-at91/pm_suspend.S.
This is necessary to disable/enable PLLA for SAM9X60 on suspend/resume.

Signed-off-by: Claudiu Beznea <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Alexandre Belloni <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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ARM: at91: pm: add pmc_version member to at91_pm_data

This will be used to differentiate b/w different PLLs settings to be
applied in the final/first steps of the suspend/resume process by doing
PLL

ARM: at91: pm: add pmc_version member to at91_pm_data

This will be used to differentiate b/w different PLLs settings to be
applied in the final/first steps of the suspend/resume process by doing
PLL specific configurations.

Signed-off-by: Claudiu Beznea <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Alexandre Belloni <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of th

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 3029 file(s).

Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Allison Randal <[email protected]>
Cc: [email protected]
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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clk: at91: master: Add sam9x60 support

The sam9x60 cpu clock is located at a different offset but is otherwise
similar to the master clock.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootl

clk: at91: master: Add sam9x60 support

The sam9x60 cpu clock is located at a different offset but is otherwise
similar to the master clock.

Signed-off-by: Alexandre Belloni <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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clk: at91: allow configuring generated PCR layout

The PCR register layout for GCLKCSS is changing for the future SoCs, allow
configuring it.

Signed-off-by: Alexandre Belloni <alexandre.belloni@boot

clk: at91: allow configuring generated PCR layout

The PCR register layout for GCLKCSS is changing for the future SoCs, allow
configuring it.

Signed-off-by: Alexandre Belloni <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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clk: at91: allow configuring peripheral PCR layout

The PCR register actually changed layout for each SoC. By chance, this
didn't have impact on sama5d[2-4] support but since sama5d3, PID is seven
bi

clk: at91: allow configuring peripheral PCR layout

The PCR register actually changed layout for each SoC. By chance, this
didn't have impact on sama5d[2-4] support but since sama5d3, PID is seven
bits wide and sama5d4 and sama5d2 don't have DIV.

For the DT backward compatibility, keep the layout as is.

Signed-off-by: Alexandre Belloni <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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ARM: at91: pm: add ULP1 support for SAM9X60

Add ULP1 support for SAM9X60. In pm_suspend.S enable RC oscillator in
PMC if it is not enabled. At resume the state before suspend is
restored.

Signed-of

ARM: at91: pm: add ULP1 support for SAM9X60

Add ULP1 support for SAM9X60. In pm_suspend.S enable RC oscillator in
PMC if it is not enabled. At resume the state before suspend is
restored.

Signed-off-by: Claudiu Beznea <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Alexandre Belloni <[email protected]>
Signed-off-by: Ludovic Desroches <[email protected]>

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ARM: at91: pm: add PMC fast startup registers defines

Add PMC fast startup registers defines.

Signed-off-by: Claudiu Beznea <[email protected]>
Signed-off-by: Alexandre Belloni <alexandr

ARM: at91: pm: add PMC fast startup registers defines

Add PMC fast startup registers defines.

Signed-off-by: Claudiu Beznea <[email protected]>
Signed-off-by: Alexandre Belloni <[email protected]>

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ARM: at91: pm: Add ULP1 mode support

In the ULP1 mode, in order to achieve the lowest power consumption
with the system in retention mode and be able to resume on the wake
up events, all the clocks

ARM: at91: pm: Add ULP1 mode support

In the ULP1 mode, in order to achieve the lowest power consumption
with the system in retention mode and be able to resume on the wake
up events, all the clocks are shut off, inclusive the embedded 12MHz
RC oscillator, and the number of wake up sources is limited as well.
When the wake up event is asserted, the embedded 12MHz RC oscillator
restarts automatically.

The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2.

The previous size of pm_suspend.o was 2148 bytes. With the addition of
ULP1 mode the new size of pm_suspend.o raised at 2456 bytes.

Signed-off-by: Wenyou Yang <[email protected]>
Signed-off-by: Ludovic Desroches <[email protected]>
[[email protected]: aligned with 4.18-rc1]
Signed-off-by: Claudiu Beznea <[email protected]>
Signed-off-by: Alexandre Belloni <[email protected]>

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clk: at91: add audio pll clock drivers

This new clock driver set allows to have a fractional divided clock that
would generate a precise clock particularly suitable for audio
applications.

The main

clk: at91: add audio pll clock drivers

This new clock driver set allows to have a fractional divided clock that
would generate a precise clock particularly suitable for audio
applications.

The main audio pll clock has two children clocks: one that is connected
to the PMC, the other that can directly drive a pad. As these two routes
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers. Each of them could modify the
rate of the main audio pll parent.

The main audio pll clock can output 620MHz to 700MHz.

Signed-off-by: Nicolas Ferre <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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clk: at91: pmc: drop at91_pmc_base

at91_pmc_base is not used anymore, remove it along with at91_pmc_read and
at91_pmc_write.

Signed-off-by: Alexandre Belloni <[email protected]>

clk: at91: pmc: drop at91_pmc_base

at91_pmc_base is not used anymore, remove it along with at91_pmc_read and
at91_pmc_write.

Signed-off-by: Alexandre Belloni <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Acked-by: Stephen Boyd <[email protected]>

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clk: at91: add generated clock driver

Add a new type of clocks that can be provided to a peripheral.
In addition to the peripheral clock, this new clock that can use several
input clocks as parents

clk: at91: add generated clock driver

Add a new type of clocks that can be provided to a peripheral.
In addition to the peripheral clock, this new clock that can use several
input clocks as parents can generate divided rates.
This would allow a peripheral to have finer grained clocks for generating
a baud rate, clocking an asynchronous part or having more
options in frequency.

Signed-off-by: Nicolas Ferre <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
[[email protected]: Transition to new clk_hw provider APIs]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: at91: add PMC sama5d2 support

Add support for the new sama5d2 SoC and adapt capabilities.

Signed-off-by: Nicolas Ferre <[email protected]>
Signed-off-by: Boris Brezillon <boris.brezillon

clk: at91: add PMC sama5d2 support

Add support for the new sama5d2 SoC and adapt capabilities.

Signed-off-by: Nicolas Ferre <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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clk: at91: cleanup PMC header file for PCR register fields

Add _MASK and _OFFSET values and cleanup register fields layout.

Signed-off-by: Nicolas Ferre <[email protected]>
Signed-off-by: Bor

clk: at91: cleanup PMC header file for PCR register fields

Add _MASK and _OFFSET values and cleanup register fields layout.

Signed-off-by: Nicolas Ferre <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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clk: at91: change to using endian agnositc IO

Change to using endian agnostic _relaxed IO accessors instead of __raw

Signed-off-by: Ben Dooks <[email protected]>
--
CC: Andrew Victor <linux

clk: at91: change to using endian agnositc IO

Change to using endian agnostic _relaxed IO accessors instead of __raw

Signed-off-by: Ben Dooks <[email protected]>
--
CC: Andrew Victor <[email protected]>
CC: Nicolas Ferre <[email protected]>
CC: Jean-Christophe Plagniol-Villard <[email protected]>
CC: Mike Turquette <[email protected]> (maintainer:COMMON CLK FRAMEWORK)
CC: Stephen Boyd <[email protected]> (maintainer:COMMON CLK FRAMEWORK)
CC: [email protected] (open list:COMMON CLK FRAMEWORK)
Signed-off-by: Michael Turquette <[email protected]>

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clk: at91: add a driver for the h32mx clock

Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix
interconnect (h32mx) has a clock that can be setup at the half of the h64mx
clock (

clk: at91: add a driver for the h32mx clock

Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix
interconnect (h32mx) has a clock that can be setup at the half of the h64mx
clock (which is mck). The h32mx clock can not exceed 90 MHz.

Signed-off-by: Alexandre Belloni <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>

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clk: at91: add slow clks driver

AT91 slow clk is a clk multiplexer.

In some SoCs (sam9x5, sama5, sam9g45 families) this multiplexer can
choose among 2 sources: an internal RC oscillator circuit and

clk: at91: add slow clks driver

AT91 slow clk is a clk multiplexer.

In some SoCs (sam9x5, sama5, sam9g45 families) this multiplexer can
choose among 2 sources: an internal RC oscillator circuit and an oscillator
using an external crystal.

In other Socs (sam9260 family) the multiplexer source is hardcoded with
the OSCSEL signal.

Signed-off-by: Boris BREZILLON <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>

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clk: at91: add PMC pll clocks

This patch adds new at91 pll clock implementation using common clk framework.

The pll clock layout describe the PLLX register layout.
There are four pll clock layouts:

clk: at91: add PMC pll clocks

This patch adds new at91 pll clock implementation using common clk framework.

The pll clock layout describe the PLLX register layout.
There are four pll clock layouts:
- at91rm9200
- at91sam9g20
- at91sam9g45
- sama5d3

PLL clocks are given characteristics:
- min/max clock source rate
- ranges of valid clock output rates
- values to set in out and icpll fields for each supported output range

These characteristics are checked during rate change to avoid
over/underclocking.

These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.

Signed-off-by: Boris BREZILLON <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>

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ARM: at91: move at91_pmc.h to include/linux/clk/at91_pmc.h

This patch moves at91_pmc.h header from machine specific directory
(arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
(i

ARM: at91: move at91_pmc.h to include/linux/clk/at91_pmc.h

This patch moves at91_pmc.h header from machine specific directory
(arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
(include/linux/clk/at91_pmc.h).
We need this to avoid reference to machine specific headers in clk
drivers.

Signed-off-by: Boris BREZILLON <[email protected]>
Acked-by: Felipe Balbi <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>

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