ACPICA: IORT: Update for revision E.f

ACPICA commit c4f5c083d24df9ddd71d5782c0988408cf0fc1ab

The IORT spec, Issue E.f (April 2024), adds a new CANWBS bit to the Memory
Access Flag field in the Memo

ACPICA: IORT: Update for revision E.f

ACPICA commit c4f5c083d24df9ddd71d5782c0988408cf0fc1ab

The IORT spec, Issue E.f (April 2024), adds a new CANWBS bit to the Memory
Access Flag field in the Memory Access Properties table, mainly for a PCI
Root Complex.

This CANWBS defines the coherency of memory accesses to be not marked IOWB
cacheable/shareable. Its value further implies the coherency impact from a
pair of mismatched memory attributes (e.g. in a nested translation case):
0x0: Use of mismatched memory attributes for accesses made by this
device may lead to a loss of coherency.
0x1: Coherency of accesses made by this device to locations in
Conventional memory are ensured as follows, even if the memory
attributes for the accesses presented by the device or provided by
the SMMU are different from Inner and Outer Write-back cacheable,
Shareable.

Link: https://github.com/acpica/acpica/commit/c4f5c083
Acked-by: Rafael J. Wysocki <[email protected]>
Signed-off-by: Nicolin Chen <[email protected]>
Acked-by: Hanjun Guo <[email protected]>
Tested-by: Nicolin Chen <[email protected]>
Reviewed-by: Jerry Snitselaar <[email protected]>
Reviewed-by: Donald Dutile <[email protected]>
Signed-off-by: Jason Gunthorpe <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Will Deacon <[email protected]>

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ACPICA: MPAM: Correct the typo in struct acpi_mpam_msc_node member

ACPICA commit 3da3f7d776d17e9bfbb15de88317de8d7397ce38

A member of the struct acpi_mpam_msc_node that represents a Memory System
C

ACPICA: MPAM: Correct the typo in struct acpi_mpam_msc_node member

ACPICA commit 3da3f7d776d17e9bfbb15de88317de8d7397ce38

A member of the struct acpi_mpam_msc_node that represents a Memory System
Controller node structure - num_resource_nodes has a typo. Fix the typo

No functional change.

Link: https://github.com/acpica/acpica/commit/3da3f7d7
Signed-off-by: Punit Agrawal <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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x86/acpi: Add support for CPU offlining for ACPI MADT wakeup method

MADT Multiprocessor Wakeup structure version 1 brings support for CPU offlining:
BIOS provides a reset vector where the CPU has to

x86/acpi: Add support for CPU offlining for ACPI MADT wakeup method

MADT Multiprocessor Wakeup structure version 1 brings support for CPU offlining:
BIOS provides a reset vector where the CPU has to jump to for offlining itself.
The new TEST mailbox command can be used to test whether the CPU offlined itself
which means the BIOS has control over the CPU and can online it again via the
ACPI MADT wakeup method.

Add CPU offlining support for the ACPI MADT wakeup method by implementing custom
cpu_die(), play_dead() and stop_this_cpu() SMP operations.

CPU offlining makes it possible to hand over secondary CPUs over kexec, not
limiting the second kernel to a single CPU.

The change conforms to the approved ACPI spec change proposal. See the Link.

Signed-off-by: Kirill A. Shutemov <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Acked-by: Kai Huang <[email protected]>
Acked-by: Rafael J. Wysocki <[email protected]>
Tested-by: Tao Liu <[email protected]>
Link: https://lore.kernel.org/all/13356251.uLZWGnKmhe@kreacher
Link: https://lore.kernel.org/r/[email protected]

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x86/acpi: Rename fields in the acpi_madt_multiproc_wakeup structure

In order to support MADT wakeup structure version 1, provide more appropriate
names for the fields in the structure.

Rename 'mail

x86/acpi: Rename fields in the acpi_madt_multiproc_wakeup structure

In order to support MADT wakeup structure version 1, provide more appropriate
names for the fields in the structure.

Rename 'mailbox_version' to 'version'. This field signifies the version of the
structure and the related protocols, rather than the version of the mailbox.
This field has not been utilized in the code thus far.

Rename 'base_address' to 'mailbox_address' to clarify the kind of address it
represents. In version 1, the structure includes the reset vector address. Clear
and distinct naming helps to prevent any confusion.

Signed-off-by: Kirill A. Shutemov <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Reviewed-by: Kai Huang <[email protected]>
Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Acked-by: Rafael J. Wysocki <[email protected]>
Tested-by: Tao Liu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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ACPICA: AEST: Add support for the AEST V2 table

ACPICA commit ebb49799c78891cbe370f1264844664a3d8b6f35

AEST V2 was published[1], add V2 support based on AEST V1.

[1]: https://developer.arm.com/doc

ACPICA: AEST: Add support for the AEST V2 table

ACPICA commit ebb49799c78891cbe370f1264844664a3d8b6f35

AEST V2 was published[1], add V2 support based on AEST V1.

[1]: https://developer.arm.com/documentation/den0085/latest/

Link: https://github.com/acpica/acpica/commit/ebb4979
Signed-off-by: Ruidong Tian <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: ACPI 6.5: RAS2: Add support for RAS2 table

ACPICA commit c581606cf49b7574d29c02b1a3bc144650375e32

Add support for ACPI RAS2 feature table(RAS2) defined in the ACPI 6.5
Specification & upwar

ACPICA: ACPI 6.5: RAS2: Add support for RAS2 table

ACPICA commit c581606cf49b7574d29c02b1a3bc144650375e32

Add support for ACPI RAS2 feature table(RAS2) defined in the ACPI 6.5
Specification & upwards revision, section 5.2.21.

The RAS2 table provides interfaces for platform RAS features. RAS2 offers
the same services as RASF, but is more scalable than the latter.
RAS2 supports independent RAS controls and capabilities for a given RAS
feature for multiple instances of the same component in a given system.
The platform can support either RAS2 or RASF but not both.

Link: https://github.com/acpica/acpica/commit/c581606c
Signed-off-by: Shiju Jose <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPI: NHLT: Streamline struct naming

Few recently introduced structs are named 'nhlt2' instead of 'nhlt' to
avoid naming conflicts. With duplicate types gone, the conflicts are no
more.

Signed-off-

ACPI: NHLT: Streamline struct naming

Few recently introduced structs are named 'nhlt2' instead of 'nhlt' to
avoid naming conflicts. With duplicate types gone, the conflicts are no
more.

Signed-off-by: Cezary Rojewski <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPI: NHLT: Drop redundant types

ACPICA commit 0c7379eae2a0342bfc36d6b7db0bb90ad13a5a3e

There are no users for the duplicated NHLT table components.

Link: https://github.com/acpica/acpica/pull/890

ACPI: NHLT: Drop redundant types

ACPICA commit 0c7379eae2a0342bfc36d6b7db0bb90ad13a5a3e

There are no users for the duplicated NHLT table components.

Link: https://github.com/acpica/acpica/pull/890
Signed-off-by: Cezary Rojewski <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPI: NHLT: Reintroduce types the table consists of

ACPICA commit 32260f5ce519e854546ce907fc0cc449e1fe51fe

Non HDAudio Link Table (NHLT) is designed to separate hardware-related
description (regist

ACPI: NHLT: Reintroduce types the table consists of

ACPICA commit 32260f5ce519e854546ce907fc0cc449e1fe51fe

Non HDAudio Link Table (NHLT) is designed to separate hardware-related
description (registers) from AudioDSP firmware-related one i.e.:
pipelines and modules that together make up the audio stream on Intel
DSPs. This task is important as same set of hardware registers can be
used with different topologies and vice versa, same topology could be
utilized with different set of hardware. As the hardware registers
description is directly tied to specific platform, intention is to have
such description part of low-level firmware e.g.: BIOS.

The initial design has been provided in early Sky Lake (SKL) days. The
audio architecture goes by the name cAVS. SKL is a representative of
cAVS 1.5. The table helps describe endpoint capabilities ever since.
While Raptor Lake (RPL) is the last of cAVS architecture - cAVS 2.5 to
be precise - its successor, the ACE architecture which begun with
Meteor Lake (MTL) inherited the design for all I2S and PDM
configurations. These two configurations are the primary targets for
NHLT table.

Due to naming conflicts with existing code, several structs are named
'nhlt2' rather than 'nhlt'. Follow up changes clean this up once
existing code has no users and is removed.

Link: https://github.com/acpica/acpica/pull/912
Signed-off-by: Cezary Rojewski <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: MADT: Add new MADT GICC/GICR/ITS non-coherent flags handling

ACPICA commit c5d2010744b1bf7efba0bd04a8a9c200ef8fb610

Add new flags and related fields to the MADT GICC/GICR/ITS
structures acc

ACPICA: MADT: Add new MADT GICC/GICR/ITS non-coherent flags handling

ACPICA commit c5d2010744b1bf7efba0bd04a8a9c200ef8fb610

Add new flags and related fields to the MADT GICC/GICR/ITS
structures according to the code first ECR:

https://bugzilla.tianocore.org/show_bug.cgi?id=4557

Update the MADT template to the latest MADT revision.

Link: https://github.com/acpica/acpica/commit/c5d20107
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: MADT: Add GICC online capable bit handling

ACPICA commit 16f0befdeddf25756f317907798192bbaa417e5e

Implement code to handle the GICC online capable bit management
added into ACPI v6.5.

Link

ACPICA: MADT: Add GICC online capable bit handling

ACPICA commit 16f0befdeddf25756f317907798192bbaa417e5e

Implement code to handle the GICC online capable bit management
added into ACPI v6.5.

Link: https://github.com/acpica/acpica/commit/16f0befd
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: RHCT: Add flags, CMO and MMU nodes

ACPICA commit 2eded5a6a13d892b7dc3be6096e7b1e8d4407600

Update RHCT table with below details.

1) Add additional structure to describe the Cache Managemen

ACPICA: RHCT: Add flags, CMO and MMU nodes

ACPICA commit 2eded5a6a13d892b7dc3be6096e7b1e8d4407600

Update RHCT table with below details.

1) Add additional structure to describe the Cache Management
Operation (CMO) related information.

2) Add structure to describe MMU type.

3) Convert the current reserved field to flags and define
a flag to indicate timer capability.

This codefirst ECR is approved by UEFI forum and will
be part of next ACPI spec version.

Link: https://github.com/acpica/acpica/commit/2eded5a6
Signed-off-by: Sunil V L <[email protected]>
Signed-off-by: Bob Moore <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: MADT: Add RISC-V external interrupt controllers

ACPICA commit 8c048cee4ea7b9ded8db3e1b3b9c14e21e084a2c

This adds 3 different external interrupt controller
definitions in MADT for RISC-V.

ACPICA: MADT: Add RISC-V external interrupt controllers

ACPICA commit 8c048cee4ea7b9ded8db3e1b3b9c14e21e084a2c

This adds 3 different external interrupt controller
definitions in MADT for RISC-V.

1) RISC-V PLIC is a platform interrupt controller for
handling wired interrupt in a RISC-V systems.

2) RISC-V IMSIC is MSI interrupt controller to
support MSI interrupts.

3) RISC-V APLIC has dual functionality. First it can
act like PLIC and direct all wired interrupts to
the CPU which doesn't have MSI controller. Second,
when the CPU has MSI controller (IMSIC), it will
act as a converter from wired interrupts to MSI.

Update the existing RINTC structure also to support
these external interrupt controllers.

This codefirst ECR is approved by UEFI forum and will
be part of next ACPI spec version.

Link: https://github.com/acpica/acpica/commit/8c048cee
Signed-off-by: Haibo, Xu <[email protected]>
Co-developed-by: Haibo, Xu <[email protected]>
Signed-off-by: Sunil V L <[email protected]>
Signed-off-by: Bob Moore <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: acpi_madt_oem_data: Fix flexible array member definition

ACPICA commit e7f6d8c1b7f79eb4b9b07f1bc09c549a2acbd6e8

Use ACPI_FLEX_ARRAY() helper to define flexible array member alone in a
struc

ACPICA: acpi_madt_oem_data: Fix flexible array member definition

ACPICA commit e7f6d8c1b7f79eb4b9b07f1bc09c549a2acbd6e8

Use ACPI_FLEX_ARRAY() helper to define flexible array member alone in a
struct. Fixes issue #812.

No binary changes appear in the .text nor .data sections.

Link: https://github.com/acpica/acpica/commit/e7f6d8c1
Signed-off-by: Bob Moore <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: struct acpi_nfit_interleave: Replace 1-element array with flexible array

ACPICA commit e66decc6fca36b59194b0947d87d6a9bec078bc3

Similar to "Replace one-element array with flexible-array", r

ACPICA: struct acpi_nfit_interleave: Replace 1-element array with flexible array

ACPICA commit e66decc6fca36b59194b0947d87d6a9bec078bc3

Similar to "Replace one-element array with flexible-array", replace the
1-element array with a proper flexible array member as defined by C99.

This allows the code to operate without tripping compile-time and run-
time bounds checkers (e.g. via __builtin_object_size(), -fsanitize=bounds,
and/or -fstrict-flex-arrays=3).

Unlike struct acpi_nfit_flush_address and struct acpi_nfit_smbios, which
had their sizeof() uses adjusted in code, struct acpi_nfit_interleave did
not. This appears to have been a bug. After this change, there is a binary
difference in acpi_dm_dump_nfit() since the size of the structure now has
the correct size, as the prior result was including the trailing U32:

- mov $0x14,%ebp
+ mov $0x10,%ebp

Link: https://github.com/acpica/acpica/commit/e66decc6
Signed-off-by: Bob Moore <[email protected]>
Reviewed-by: Dan Williams <[email protected]>
Tested-by: Dan Williams <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: actbl2: Replace 1-element arrays with flexible arrays

ACPICA commit 44f1af0664599e87bebc3a1260692baa27b2f264

Similar to "Replace one-element array with flexible-array", replace the
1-elemen

ACPICA: actbl2: Replace 1-element arrays with flexible arrays

ACPICA commit 44f1af0664599e87bebc3a1260692baa27b2f264

Similar to "Replace one-element array with flexible-array", replace the
1-element array with a proper flexible array member as defined by C99.

This allows the code to operate without tripping compile-time and run-
time bounds checkers (e.g. via __builtin_object_size(), -fsanitize=bounds,
and/or -fstrict-flex-arrays=3).

The sizeof() uses with struct acpi_nfit_flush_address and struct
acpi_nfit_smbios have been adjusted to drop the open-coded subtraction
of the trailing single element. The result is no binary differences in
.text nor .data sections.

Link: https://github.com/acpica/acpica/commit/44f1af06
Signed-off-by: Bob Moore <[email protected]>
Co-developed-by: Dan Williams <[email protected]>
Signed-off-by: Dan Williams <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: Add structure definitions for RISC-V RHCT

ACPICA commit 82afd0434e79f74b96a6be88115ddc8343a1ba40

RISC-V Hart Capabilities Table (RHCT) is a new static table.
The ECR to add RHCT is approved

ACPICA: Add structure definitions for RISC-V RHCT

ACPICA commit 82afd0434e79f74b96a6be88115ddc8343a1ba40

RISC-V Hart Capabilities Table (RHCT) is a new static table.
The ECR to add RHCT is approved by the UEFI forum and will be
available in the next version of the ACPI spec.

Link: https://github.com/acpica/acpica/commit/82afd043
Signed-off-by: Sunil V L <[email protected]>
Signed-off-by: Bob Moore <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: MADT: Add RISC-V INTC interrupt controller

ACPICA commit bd6d1ae1e13abe78e149c8b61b4bc7bc7feab015

The ECR to add RISC-V INTC interrupt controller is approved by
the UEFI forum and will be a

ACPICA: MADT: Add RISC-V INTC interrupt controller

ACPICA commit bd6d1ae1e13abe78e149c8b61b4bc7bc7feab015

The ECR to add RISC-V INTC interrupt controller is approved by
the UEFI forum and will be available in the next revision of
the ACPI specification.

Link: https://github.com/acpica/acpica/commit/bd6d1ae1
Signed-off-by: Sunil V L <[email protected]>
Signed-off-by: Bob Moore <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: Update all copyrights/signons to 2023

ACPICA commit 25bddd1824b1e450829468a64bbdcb38074ba3d2

Copyright updates to 2023.

Link: https://github.com/acpica/acpica/commit/25bddd18
Signed-off-by

ACPICA: Update all copyrights/signons to 2023

ACPICA commit 25bddd1824b1e450829468a64bbdcb38074ba3d2

Copyright updates to 2023.

Link: https://github.com/acpica/acpica/commit/25bddd18
Signed-off-by: Bob Moore <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: Add support for Arm's MPAM ACPI table version 2

ACPICA commit 005e24bcaa6e4c7db327b4f81fb63b2715aac7e6

Complies with ACPI for Memory System Resource Partitioning and
Monitoring 2.0 [1]. Doc

ACPICA: Add support for Arm's MPAM ACPI table version 2

ACPICA commit 005e24bcaa6e4c7db327b4f81fb63b2715aac7e6

Complies with ACPI for Memory System Resource Partitioning and
Monitoring 2.0 [1]. Document number: DEN0065, as of December 2022.

Support for all types of MPAM resources. No support yet for:
1) MPAM PCC Interface Type
2) The optional Resource-specific data per MSC node, introduced in v2 of the
MPAM ACPI spec.

[1] https://developer.arm.com/documentation/den0065/latest

Link: https://github.com/acpica/acpica/commit/005e24bc
Signed-off-by: Hesham Almatary <[email protected]>
Signed-off-by: Bob Moore <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: ACPI 6.5: MADT: add support for trace buffer extension in GICC

ACPICA commit 1363e35dc6976143d118588b5124d72017365588

Link: https://github.com/acpica/acpica/commit/1363e35d
Signed-off-by: X

ACPICA: ACPI 6.5: MADT: add support for trace buffer extension in GICC

ACPICA commit 1363e35dc6976143d118588b5124d72017365588

Link: https://github.com/acpica/acpica/commit/1363e35d
Signed-off-by: Xiongfeng Wang <[email protected]>
Signed-off-by: Bob Moore <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: Headers: Delete bogus node_array array of pointers from AEST table

ACPICA commit f0c4a06f1dfc4886d4e0c2aa30bc57b10c5a8c53

Like many tables, this is a header followed by multiple subtables o

ACPICA: Headers: Delete bogus node_array array of pointers from AEST table

ACPICA commit f0c4a06f1dfc4886d4e0c2aa30bc57b10c5a8c53

Like many tables, this is a header followed by multiple subtables of
varying self-identifying types, and ACPICA does not normally add a field
for the subtables, instead relying on pointer arithmetic past the end of
the first header struct, since indexing a flexible array member is
meaningless for variable-length entries. If we really wanted a field for
this, we could use a u8 flexible array member, but it contradicts the
current style. Using void *, however, is categorically wrong, as ACPI
tables never contain native C-language pointers.

Link: https://github.com/acpica/acpica/commit/f0c4a06f
Signed-off-by: Bob Moore <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: Finish support for the CDAT table

ACPICA commit 8ac4e5116f59d6f9ba2fbeb9ce22ab58237a278f

Finish support for the CDAT table, in both the data table compiler and
the disassembler.

Link: http

ACPICA: Finish support for the CDAT table

ACPICA commit 8ac4e5116f59d6f9ba2fbeb9ce22ab58237a278f

Finish support for the CDAT table, in both the data table compiler and
the disassembler.

Link: https://github.com/acpica/acpica/commit/8ac4e511
Signed-off-by: Bob Moore <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: IORT: Update for revision E.e

ACPICA commit 54b54732c5fc9e0384bcfd531f3c10d3a7b628b5

The latest IORT update makes one small addition to SMMUv3 nodes to
describe MSI support independently of

ACPICA: IORT: Update for revision E.e

ACPICA commit 54b54732c5fc9e0384bcfd531f3c10d3a7b628b5

The latest IORT update makes one small addition to SMMUv3 nodes to
describe MSI support independently of wired GSIV support.

Link: https://github.com/acpica/acpica/commit/54b54732
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Bob Moore <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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ACPICA: iASL: Add CCEL table to both compiler/disassembler

ACPICA commit 10e4763f155eac0c60295a7e364b0316fc52c4f1

Link: https://github.com/acpica/acpica/commit/10e4763f
Signed-off-by: Kuppuswamy Sa

ACPICA: iASL: Add CCEL table to both compiler/disassembler

ACPICA commit 10e4763f155eac0c60295a7e364b0316fc52c4f1

Link: https://github.com/acpica/acpica/commit/10e4763f
Signed-off-by: Kuppuswamy Sathyanarayanan <[email protected]>
Signed-off-by: Bob Moore <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>

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