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Revision tags: v6.15, v6.15-rc7, v6.15-rc6, v6.15-rc5, v6.15-rc4, v6.15-rc3, v6.15-rc2, v6.15-rc1, v6.14, v6.14-rc7, v6.14-rc6, v6.14-rc5, v6.14-rc4, v6.14-rc3, v6.14-rc2, v6.14-rc1, v6.13, v6.13-rc7, v6.13-rc6, v6.13-rc5, v6.13-rc4, v6.13-rc3, v6.13-rc2, v6.13-rc1, v6.12, v6.12-rc7, v6.12-rc6, v6.12-rc5, v6.12-rc4, v6.12-rc3, v6.12-rc2, v6.12-rc1, v6.11 |
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| #
6eab0ce6 |
| 09-Sep-2024 |
Nikita Shubin <[email protected]> |
soc: Add SoC driver for Cirrus ep93xx
Add an SoC driver for the ep93xx. Currently there is only one thing not fitting into any other framework, and that is the swlock setting.
Used for clock settin
soc: Add SoC driver for Cirrus ep93xx
Add an SoC driver for the ep93xx. Currently there is only one thing not fitting into any other framework, and that is the swlock setting.
Used for clock settings, pinctrl and restart.
Signed-off-by: Nikita Shubin <[email protected]> Tested-by: Alexander Sverdlin <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Acked-by: Alexander Sverdlin <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
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Revision tags: v6.11-rc7, v6.11-rc6, v6.11-rc5, v6.11-rc4, v6.11-rc3, v6.11-rc2, v6.11-rc1, v6.10, v6.10-rc7, v6.10-rc6, v6.10-rc5, v6.10-rc4, v6.10-rc3, v6.10-rc2, v6.10-rc1, v6.9, v6.9-rc7, v6.9-rc6, v6.9-rc5, v6.9-rc4, v6.9-rc3, v6.9-rc2, v6.9-rc1, v6.8, v6.8-rc7, v6.8-rc6, v6.8-rc5, v6.8-rc4, v6.8-rc3, v6.8-rc2, v6.8-rc1, v6.7, v6.7-rc8, v6.7-rc7, v6.7-rc6, v6.7-rc5, v6.7-rc4, v6.7-rc3, v6.7-rc2, v6.7-rc1, v6.6, v6.6-rc7, v6.6-rc6 |
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| #
971f128b |
| 12-Oct-2023 |
Conor Dooley <[email protected]> |
soc: sifive: shunt ccache driver to drivers/cache
Move the ccache driver over to drivers/cache, out of the drivers/soc dumping ground, to this new collection point for cache controller drivers.
Rev
soc: sifive: shunt ccache driver to drivers/cache
Move the ccache driver over to drivers/cache, out of the drivers/soc dumping ground, to this new collection point for cache controller drivers.
Reviewed-by: Samuel Holland <[email protected]> Tested-by: Samuel Holland <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
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Revision tags: v6.6-rc5, v6.6-rc4, v6.6-rc3, v6.6-rc2 |
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ac68b50d |
| 12-Sep-2023 |
Ulf Hansson <[email protected]> |
pmdomain: starfive: Move Kconfig file to the pmdomain subsystem
The Kconfig belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem.
pmdomain: starfive: Move Kconfig file to the pmdomain subsystem
The Kconfig belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem.
Cc: Walker Chen <[email protected]> Cc: Conor Dooley <[email protected]> Acked-by: Conor Dooley <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
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4db57046 |
| 11-Sep-2023 |
Ulf Hansson <[email protected]> |
pmdomain: actions: Move Kconfig file to the pmdomain subsystem
The Kconfig belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem.
pmdomain: actions: Move Kconfig file to the pmdomain subsystem
The Kconfig belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem.
Cc: "Andreas Färber" <[email protected]> Cc: Manivannan Sadhasivam <[email protected]> Cc: <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
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Revision tags: v6.6-rc1, v6.5, v6.5-rc7, v6.5-rc6 |
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886bdf9c |
| 08-Aug-2023 |
Huisong Li <[email protected]> |
soc: hisilicon: Support HCCS driver on Kunpeng SoC
The Huawei Cache Coherence System (HCCS) is a multi-chip interconnection bus protocol. This driver is aimed to support some features about HCCS on
soc: hisilicon: Support HCCS driver on Kunpeng SoC
The Huawei Cache Coherence System (HCCS) is a multi-chip interconnection bus protocol. This driver is aimed to support some features about HCCS on Kunpeng SoC, like, querying the health status of HCCS.
This patch adds the probing of HCCS driver, and obtains all HCCS port information by the dimension of chip and die on platform.
Signed-off-by: Huisong Li <[email protected]> Signed-off-by: Wei Xu <[email protected]>
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Revision tags: v6.5-rc5, v6.5-rc4, v6.5-rc3, v6.5-rc2, v6.5-rc1, v6.4, v6.4-rc7, v6.4-rc6, v6.4-rc5, v6.4-rc4, v6.4-rc3, v6.4-rc2, v6.4-rc1, v6.3, v6.3-rc7, v6.3-rc6, v6.3-rc5, v6.3-rc4, v6.3-rc3, v6.3-rc2, v6.3-rc1, v6.2, v6.2-rc8, v6.2-rc7 |
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7dbb4a38 |
| 01-Feb-2023 |
Jonathan Neuschäfer <[email protected]> |
soc: nuvoton: Add SoC info driver for WPCM450
Add a SoC information driver for Nuvoton WPCM450 SoCs. It provides information such as the SoC revision.
Usage example:
# grep . /sys/devices/soc0/*
soc: nuvoton: Add SoC info driver for WPCM450
Add a SoC information driver for Nuvoton WPCM450 SoCs. It provides information such as the SoC revision.
Usage example:
# grep . /sys/devices/soc0/* /sys/devices/soc0/family:Nuvoton NPCM /sys/devices/soc0/revision:A3 /sys/devices/soc0/soc_id:WPCM450
Signed-off-by: Jonathan Neuschäfer <[email protected]> Reviewed-by: Joel Stanley <[email protected]> Reviewed-by: Paul Menzel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joel Stanley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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Revision tags: v6.2-rc6, v6.2-rc5 |
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08b9a94e |
| 19-Jan-2023 |
Walker Chen <[email protected]> |
soc: starfive: Add StarFive JH71XX pmu driver
Add pmu driver for the StarFive JH71XX SoC.
As the power domains provider, the Power Management Unit (PMU) is designed for including multiple PM domain
soc: starfive: Add StarFive JH71XX pmu driver
Add pmu driver for the StarFive JH71XX SoC.
As the power domains provider, the Power Management Unit (PMU) is designed for including multiple PM domains that can be used for power gating of selected IP blocks for power saving by reduced leakage current. It accepts software encourage command to switch the power mode of SoC.
Signed-off-by: Walker Chen <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
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Revision tags: v6.2-rc4, v6.2-rc3, v6.2-rc2, v6.2-rc1, v6.1, v6.1-rc8, v6.1-rc7, v6.1-rc6, v6.1-rc5 |
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b82621ac |
| 11-Nov-2022 |
Yinbo Zhu <[email protected]> |
soc: loongson: add GUTS driver for loongson-2 platforms
The global utilities block controls PCIE device enabling, alternate function selection for multiplexed signals, consistency of HDA, USB and PC
soc: loongson: add GUTS driver for loongson-2 platforms
The global utilities block controls PCIE device enabling, alternate function selection for multiplexed signals, consistency of HDA, USB and PCIE, configuration of memory controller, rtc controller, lio controller, and clock control.
This patch adds a driver to manage and access global utilities block for LoongArch architecture Loongson-2 SoCs. Initially only reading SVR and registering soc device are supported. Other guts accesses, such as reading firmware configuration by default, should eventually be added into this driver as well.
Signed-off-by: Yinbo Zhu <[email protected]> Reviewed-by: Arnd Bergmann <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
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Revision tags: v6.1-rc4, v6.1-rc3, v6.1-rc2, v6.1-rc1, v6.0, v6.0-rc7, v6.0-rc6, v6.0-rc5, v6.0-rc4, v6.0-rc3, v6.0-rc2, v6.0-rc1, v5.19, v5.19-rc8, v5.19-rc7, v5.19-rc6, v5.19-rc5, v5.19-rc4, v5.19-rc3, v5.19-rc2, v5.19-rc1, v5.18 |
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64f89dfa |
| 20-May-2022 |
Hitomi Hasegawa <[email protected]> |
soc: fujitsu: Add A64FX diagnostic interrupt driver
Register the NMI/IRQ corresponding to the A64FX's device definition dedicated to diagnostic interrupts, so that when this interrupt is sent using
soc: fujitsu: Add A64FX diagnostic interrupt driver
Register the NMI/IRQ corresponding to the A64FX's device definition dedicated to diagnostic interrupts, so that when this interrupt is sent using the BMC, it causes a panic. This can be used to obtain a kernel dump.
Signed-off-by: Hitomi Hasegawa <[email protected]> Link: https://lore.kernel.org/r/[email protected]' Signed-off-by: Arnd Bergmann <[email protected]>
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Revision tags: v5.18-rc7, v5.18-rc6, v5.18-rc5, v5.18-rc4, v5.18-rc3, v5.18-rc2, v5.18-rc1, v5.17, v5.17-rc8, v5.17-rc7, v5.17-rc6, v5.17-rc5, v5.17-rc4, v5.17-rc3, v5.17-rc2, v5.17-rc1, v5.16, v5.16-rc8, v5.16-rc7, v5.16-rc6, v5.16-rc5, v5.16-rc4, v5.16-rc3, v5.16-rc2, v5.16-rc1, v5.15, v5.15-rc7, v5.15-rc6, v5.15-rc5, v5.15-rc4, v5.15-rc3, v5.15-rc2, v5.15-rc1, v5.14, v5.14-rc7, v5.14-rc6, v5.14-rc5, v5.14-rc4, v5.14-rc3, v5.14-rc2, v5.14-rc1, v5.13, v5.13-rc7, v5.13-rc6, v5.13-rc5, v5.13-rc4, v5.13-rc3, v5.13-rc2, v5.13-rc1, v5.12, v5.12-rc8, v5.12-rc7, v5.12-rc6, v5.12-rc5, v5.12-rc4, v5.12-rc3, v5.12-rc2, v5.12-rc1, v5.12-rc1-dontuse, v5.11, v5.11-rc7, v5.11-rc6, v5.11-rc5, v5.11-rc4, v5.11-rc3, v5.11-rc2, v5.11-rc1, v5.10, v5.10-rc7, v5.10-rc6, v5.10-rc5, v5.10-rc4, v5.10-rc3, v5.10-rc2, v5.10-rc1, v5.9, v5.9-rc8, v5.9-rc7, v5.9-rc6, v5.9-rc5, v5.9-rc4, v5.9-rc3, v5.9-rc2, v5.9-rc1, v5.8, v5.8-rc7, v5.8-rc6, v5.8-rc5, v5.8-rc4, v5.8-rc3, v5.8-rc2, v5.8-rc1, v5.7, v5.7-rc7, v5.7-rc6, v5.7-rc5, v5.7-rc4, v5.7-rc3, v5.7-rc2, v5.7-rc1, v5.6, v5.6-rc7, v5.6-rc6, v5.6-rc5, v5.6-rc4, v5.6-rc3, v5.6-rc2, v5.6-rc1, v5.5, v5.5-rc7, v5.5-rc6, v5.5-rc5, v5.5-rc4, v5.5-rc3, v5.5-rc2, v5.5-rc1, v5.4, v5.4-rc8, v5.4-rc7, v5.4-rc6, v5.4-rc5, v5.4-rc4, v5.4-rc3, v5.4-rc2, v5.4-rc1 |
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| #
64dbc4dd |
| 20-Sep-2019 |
Arnd Bergmann <[email protected]> |
ARM: pxa: move plat-pxa to drivers/soc/
There are two drivers in arch/arm/plat-pxa: mfp and ssp. Both of them should ideally not be needed at all, as there are proper subsystems to replace them.
OT
ARM: pxa: move plat-pxa to drivers/soc/
There are two drivers in arch/arm/plat-pxa: mfp and ssp. Both of them should ideally not be needed at all, as there are proper subsystems to replace them.
OTOH, they are self-contained and can simply be normal SoC drivers, so move them over there to eliminate one more of the plat-* directories.
Acked-by: Robert Jarzmik <[email protected]> (mach-pxa) Acked-by: Lubomir Rintel <[email protected]> (mach-mmp) Signed-off-by: Arnd Bergmann <[email protected]>
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d0054a47 |
| 17-Feb-2022 |
Conor Dooley <[email protected]> |
soc: add microchip polarfire soc system controller
This driver provides an interface for other drivers to access the functions of the system controller on the Microchip PolarFire SoC.
Signed-off-by
soc: add microchip polarfire soc system controller
This driver provides an interface for other drivers to access the functions of the system controller on the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <[email protected]> Signed-off-by: Nicolas Ferre <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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6df9d38f |
| 24-Nov-2021 |
Hector Martin <[email protected]> |
soc: apple: Add driver for Apple PMGR power state controls
Implements genpd and reset providers for downstream devices. Each instance of the driver binds to a single register and represents a single
soc: apple: Add driver for Apple PMGR power state controls
Implements genpd and reset providers for downstream devices. Each instance of the driver binds to a single register and represents a single SoC power domain.
The driver does not currently implement all features (clockgate-only state, misc flags), but we declare the respective registers for documentation purposes. These features will be added as they become useful for downstream devices.
This also creates the apple/soc tree and Kconfig submenu.
Acked-by: Linus Walleij <[email protected]> Signed-off-by: Hector Martin <[email protected]>
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89d4f98a |
| 18-Jan-2021 |
Arnd Bergmann <[email protected]> |
ARM: remove zte zx platform
The ZTE ZX set-top-box SoC platform was added in 2015 by Jun Nie, with Baoyou Xie and Shawn Guo subsequently becoming maintainers after the addition of the 64-bit variant
ARM: remove zte zx platform
The ZTE ZX set-top-box SoC platform was added in 2015 by Jun Nie, with Baoyou Xie and Shawn Guo subsequently becoming maintainers after the addition of the 64-bit variant.
However, the only machines that were ever supported upstream are the reference designs, not actual set-top-box devices that would benefit from this support. All ZTE set-top-boxes from the past few years seem to be based on third-party SoCs. While there is very little information about zx296702 and zx296718 on the web, I found some references to other chips from the same family, such as zx296716 and zx296719, which were never submitted for upstream support. Finally, there is no support for the GPU on either of them, with the lima and panfrost device drivers having been added after work on the zx platform had stopped.
Shawn confirmed that he has not seen any interest in this platform for the past four years, and that it can be removed.
Thanks to Jun and Shawn for maintaining this platform over the past five years.
Cc: Jun Nie <[email protected]> Cc: Shawn Guo <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
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08734e05 |
| 13-Dec-2020 |
Damien Le Moal <[email protected]> |
riscv: Use vendor name for K210 SoC support
Rename configuration options and directories related to the Kendryte K210 SoC to use the SoC vendor name (canaan) instead of the "kendryte" branding name.
riscv: Use vendor name for K210 SoC support
Rename configuration options and directories related to the Kendryte K210 SoC to use the SoC vendor name (canaan) instead of the "kendryte" branding name.
Signed-off-by: Damien Le Moal <[email protected]> Reviewed-by: Anup Patel <[email protected]> Signed-off-by: Palmer Dabbelt <[email protected]>
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22447a99 |
| 13-Oct-2020 |
Pawel Czarnecki <[email protected]> |
drivers/soc/litex: add LiteX SoC Controller driver
This commit adds driver for the FPGA-based LiteX SoC Controller from LiteX SoC builder.
Co-developed-by: Mateusz Holenko <[email protected]> S
drivers/soc/litex: add LiteX SoC Controller driver
This commit adds driver for the FPGA-based LiteX SoC Controller from LiteX SoC builder.
Co-developed-by: Mateusz Holenko <[email protected]> Signed-off-by: Mateusz Holenko <[email protected]> Signed-off-by: Pawel Czarnecki <[email protected]> Signed-off-by: Stafford Horne <[email protected]>
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c48c4a4c |
| 16-Mar-2020 |
Christoph Hellwig <[email protected]> |
riscv: Add Kendryte K210 SoC support
Add support for the Kendryte K210 RISC-V SoC. For now, this support only provides a simple sysctl driver allowing to setup the CPU and uart clock. This support i
riscv: Add Kendryte K210 SoC support
Add support for the Kendryte K210 RISC-V SoC. For now, this support only provides a simple sysctl driver allowing to setup the CPU and uart clock. This support is enabled through the new Kconfig option SOC_KENDRYTE and defines the config option CONFIG_K210_SYSCTL to enable the K210 SoC sysctl driver compilation.
The sysctl driver also registers an early SoC initialization function allowing enabling the general purpose use of the 2MB of SRAM normally reserved for the SoC AI engine. This initialization function is automatically called before the dt early initialization using the flat dt root node compatible property matching the value "kendryte,k210".
Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Damien Le Moal <[email protected]> [Palmer: Add missing endmenu in Kconfig.socs] Signed-off-by: Palmer Dabbelt <[email protected]>
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9209fb51 |
| 07-Nov-2019 |
Christoph Hellwig <[email protected]> |
riscv: move sifive_l2_cache.c to drivers/soc
The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC ma
riscv: move sifive_l2_cache.c to drivers/soc
The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC maintainers prefer their drivers to be structured in a certain way that doesn't fit the SiFive SOCs.
Move the file to drivers/soc and add a Kconfig option for it, as well as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.
Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Christoph Hellwig <[email protected]> Reviewed-by: Borislav Petkov <[email protected]> [[email protected]: keep the MAINTAINERS change specific to the L2$ controller code] Signed-off-by: Paul Walmsley <[email protected]>
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Revision tags: v5.3, v5.3-rc8, v5.3-rc7, v5.3-rc6, v5.3-rc5, v5.3-rc4, v5.3-rc3, v5.3-rc2, v5.3-rc1, v5.2, v5.2-rc7, v5.2-rc6, v5.2-rc5, v5.2-rc4, v5.2-rc3, v5.2-rc2, v5.2-rc1 |
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ec8f24b7 |
| 19-May-2019 |
Thomas Gleixner <[email protected]> |
treewide: Add SPDX license identifier - Makefile/Kconfig
Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project
treewide: Add SPDX license identifier - Makefile/Kconfig
Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is:
GPL-2.0-only
Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Revision tags: v5.1, v5.1-rc7 |
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524feb79 |
| 22-Apr-2019 |
Patrick Venture <[email protected]> |
soc: add aspeed folder and misc drivers
Create a SoC folder for the ASPEED parts and place the misc drivers currently present into this folder. These drivers are not generic part drivers, but rathe
soc: add aspeed folder and misc drivers
Create a SoC folder for the ASPEED parts and place the misc drivers currently present into this folder. These drivers are not generic part drivers, but rather only apply to the ASPEED SoCs.
Signed-off-by: Patrick Venture <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
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Revision tags: v5.1-rc6, v5.1-rc5, v5.1-rc4, v5.1-rc3, v5.1-rc2, v5.1-rc1, v5.0, v5.0-rc8, v5.0-rc7, v5.0-rc6 |
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fcf2d897 |
| 10-Feb-2019 |
Linus Walleij <[email protected]> |
ARM: ixp4xx: Move NPE and QMGR to drivers/soc
The Network Processing Engine and Queue Manager are versatile firmware components used by several IXP4xx drivers.
Drivers are relying on getting access
ARM: ixp4xx: Move NPE and QMGR to drivers/soc
The Network Processing Engine and Queue Manager are versatile firmware components used by several IXP4xx drivers.
Drivers are relying on getting access to these components using <mach/*> headers which does not work with multiplatform. We need to find a better place for the drivers to live.
Let's first move them to drivers/soc and the start to refactor a bit by passing resources and moving headers.
This patch introduce static IRQ assignments but that will be fixed by later patches in this series.
Signed-off-by: Linus Walleij <[email protected]>
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Revision tags: v5.0-rc5, v5.0-rc4, v5.0-rc3, v5.0-rc2, v5.0-rc1, v4.20, v4.20-rc7, v4.20-rc6, v4.20-rc5, v4.20-rc4, v4.20-rc3, v4.20-rc2, v4.20-rc1, v4.19, v4.19-rc8, v4.19-rc7, v4.19-rc6, v4.19-rc5, v4.19-rc4, v4.19-rc3, v4.19-rc2, v4.19-rc1, v4.18, v4.18-rc8, v4.18-rc7, v4.18-rc6, v4.18-rc5, v4.18-rc4, v4.18-rc3, v4.18-rc2, v4.18-rc1, v4.17, v4.17-rc7, v4.17-rc6, v4.17-rc5, v4.17-rc4, v4.17-rc3, v4.17-rc2, v4.17-rc1, v4.16, v4.16-rc7, v4.16-rc6, v4.16-rc5, v4.16-rc4, v4.16-rc3, v4.16-rc2, v4.16-rc1, v4.15, v4.15-rc9, v4.15-rc8, v4.15-rc7, v4.15-rc6, v4.15-rc5 |
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| #
5abcdc20 |
| 19-Dec-2017 |
Michal Simek <[email protected]> |
soc: xilinx: Create folder structure for soc specific drivers
Create directory structure with Makefile/Kconfig for adding xilinx soc specific drivers.
Signed-off-by: Michal Simek <michal.simek@xili
soc: xilinx: Create folder structure for soc specific drivers
Create directory structure with Makefile/Kconfig for adding xilinx soc specific drivers.
Signed-off-by: Michal Simek <[email protected]>
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Revision tags: v4.15-rc4, v4.15-rc3, v4.15-rc2, v4.15-rc1, v4.14, v4.14-rc8, v4.14-rc7, v4.14-rc6, v4.14-rc5, v4.14-rc4, v4.14-rc3, v4.14-rc2, v4.14-rc1, v4.13, v4.13-rc7, v4.13-rc6, v4.13-rc5, v4.13-rc4, v4.13-rc3, v4.13-rc2, v4.13-rc1, v4.12, v4.12-rc7 |
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| #
a9daaba2 |
| 23-Jun-2017 |
Neil Armstrong <[email protected]> |
soc: Add Amlogic SoC Information driver
Amlogic SoCs have a SoC information register for SoC type, package type and revision information. This patchs adds support for this register decoding and expo
soc: Add Amlogic SoC Information driver
Amlogic SoCs have a SoC information register for SoC type, package type and revision information. This patchs adds support for this register decoding and exposing with the SoC bus infrastructure.
Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
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Revision tags: v4.12-rc6, v4.12-rc5, v4.12-rc4, v4.12-rc3, v4.12-rc2, v4.12-rc1, v4.11, v4.11-rc8, v4.11-rc7, v4.11-rc6, v4.11-rc5, v4.11-rc4, v4.11-rc3, v4.11-rc2, v4.11-rc1 |
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aa9f800d |
| 26-Feb-2017 |
Andreas Färber <[email protected]> |
soc: actions: Add Owl SPS
Implement S500 Smart Power System power-gating. For now flag PD_CPU2 and PD_CPU3 as always-on.
Based on LeMaker linux-actions tree.
Signed-off-by: Andreas Färber <afaerbe
soc: actions: Add Owl SPS
Implement S500 Smart Power System power-gating. For now flag PD_CPU2 and PD_CPU3 as always-on.
Based on LeMaker linux-actions tree.
Signed-off-by: Andreas Färber <[email protected]>
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8be381a1 |
| 19-May-2017 |
Geert Uytterhoeven <[email protected]> |
soc: renesas: Rework Kconfig and Makefile logic
The goals are to: - Allow precise control over and automatic selection of which (sub)drivers are used for which SoC, - Allow adding support fo
soc: renesas: Rework Kconfig and Makefile logic
The goals are to: - Allow precise control over and automatic selection of which (sub)drivers are used for which SoC, - Allow adding support for new SoCs easily, - Allow compile-testing of all (sub)drivers, - Keep driver selection logic in the subsystem-specific Kconfig, independent from the architecture-specific Kconfig (i.e. no "select" from arch/arm64/Kconfig.platforms), to avoid dependencies.
This is implemented by: - Introducing Kconfig symbols for all drivers and sub-drivers, - Introducing the Kconfig symbol SOC_RENESAS, which is enabled automatically when building for a Renesas ARM platform, and which enables all required drivers without interaction of the user, based on SoC-specific ARCH_* symbols, - Allowing the user to enable any Kconfig symbol manually if COMPILE_TEST is enabled, - Using the new Kconfig symbols instead of the ARCH_* symbols to control compilation in the Makefile, - Always entering drivers/soc/renesas/ during the build.
Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Simon Horman <[email protected]>
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03aa1262 |
| 28-Mar-2017 |
Andrey Smirnov <[email protected]> |
soc: imx: Add GPCv2 power gating driver
Add code allowing for control of various power domains managed by GPCv2 IP block found in i.MX7 series of SoCs. Power domains covered by this patch are:
soc: imx: Add GPCv2 power gating driver
Add code allowing for control of various power domains managed by GPCv2 IP block found in i.MX7 series of SoCs. Power domains covered by this patch are:
- PCIE PHY - MIPI PHY - USB HSIC PHY - USB OTG1/2 PHY
Support for any other power domain controlled by GPC is not present, and can be added at some later point.
Testing of this code was done against a PCIe driver.
Cc: [email protected] Cc: Lucas Stach <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Dong Aisheng <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Andrey Smirnov <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
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