pinctrl: sunxi: Add support for the secondary A523 GPIO ports

As most other Allwinner SoCs before, the A523 chip contains a second
GPIO controller, managing banks PL and PM.
Use the newly introduced

pinctrl: sunxi: Add support for the secondary A523 GPIO ports

As most other Allwinner SoCs before, the A523 chip contains a second
GPIO controller, managing banks PL and PM.
Use the newly introduced DT based pinctrl driver to describe just the
generic pinctrl properties, so advertise the number of pins per bank
and the interrupt capabilities. The actual function/mux assignment is
taken from the devicetree.

Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add support for the Allwinner A523

The Allwinner A523 contains pins in 10 out of the 11 possible pin banks;
it just skips port A.
Use the newly introduced DT based pinctrl driver to

pinctrl: sunxi: Add support for the Allwinner A523

The Allwinner A523 contains pins in 10 out of the 11 possible pin banks;
it just skips port A.
Use the newly introduced DT based pinctrl driver to describe just the
generic pinctrl properties, so advertise the number of pins per bank
and the interrupt capabilities. The actual function/mux assignment is
taken from the devicetree.

Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: allow reading mux values from DT

So far every Allwinner SoC needs a large table in the kernel code, to
describe the mapping between the pinctrl function names ("uart") and
the actual

pinctrl: sunxi: allow reading mux values from DT

So far every Allwinner SoC needs a large table in the kernel code, to
describe the mapping between the pinctrl function names ("uart") and
the actual pincontroller mux value to be written into the registers.
This adds a lot of data into a single image kernel, and also looks
somewhat weird, as the DT can easily store the mux value.

Add some code that allows to avoid that table: the struct that describes
the existing pins will be build at *runtime*, based on very basic
information provided by the respective SoC's pinctrl driver. This
consists of the number of pins per bank, plus information which bank
provides IRQ support, along with the mux value to use for that.
The code will then iterate over all children of the pincontroller DT
node (which describe each pin group), and populate that struct with the
mapping between function names and mux values. The only thing that needs
adding in the DT is a property with that value, per pin group.

When this table is built, it will be handed over to the existing sunxi
pinctrl driver, which cannot tell a difference between a hardcoded
struct and this new one built at runtime. It will take care of
registering the pinctrl device with the pinctrl subsystem.

All a new SoC driver would need to do is to provide two arrays, and then
call the sunxi_pinctrl_dt_table_init() function.

Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add driver for Allwinner D1

This SoC contains a pinctrl with a new register layout. Use the variant
parameter to set the right register offsets. This pinctrl also increases
the numbe

pinctrl: sunxi: Add driver for Allwinner D1

This SoC contains a pinctrl with a new register layout. Use the variant
parameter to set the right register offsets. This pinctrl also increases
the number of functions per pin from 8 to 16, taking advantage of all 4
bits in the mux config field (so far, only functions 0-8 and 14-15 are
used). This increases the maximum possible number of functions.

Reviewed-by: Heiko Stuebner <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add support for the Allwinner H616-R pin controller

There are only two pins left now, used to connect to the PMIC via I2C.

Signed-off-by: Andre Przywara <[email protected]>
Ack

pinctrl: sunxi: Add support for the Allwinner H616-R pin controller

There are only two pins left now, used to connect to the PMIC via I2C.

Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add support for the Allwinner H616 pin controller

Port A is used for an internal connection to some analogue circuitry
which looks like an AC200 IP (as in the H6), though this is not

pinctrl: sunxi: Add support for the Allwinner H616 pin controller

Port A is used for an internal connection to some analogue circuitry
which looks like an AC200 IP (as in the H6), though this is not
mentioned in the manual.

Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: add support for the Allwinner A100 pin controller

This commit introduces support for the pin controller on A100.

Signed-off-by: Yangtao Li <[email protected]>
Acked-by: Maxime

pinctrl: sunxi: add support for the Allwinner A100 pin controller

This commit introduces support for the pin controller on A100.

Signed-off-by: Yangtao Li <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Link: https://lore.kernel.org/r/4e331a2ed4a30c883df6157bc5c52bb686aa8e0d.1595572867.git.frank@allwinnertech.com
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)

The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a
pin
controller like other SoCs from Allwinner.

Add support

pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)

The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a
pin
controller like other SoCs from Allwinner.

Add support for it.

Signed-off-by: Mesih Kilinc <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: add support for H6 R_PIO pin controller

Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs,
which controls the PL and PM pin banks.

Add support for it.

Signed-of

pinctrl: sunxi: add support for H6 R_PIO pin controller

Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs,
which controls the PL and PM pin banks.

Add support for it.

Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: add support for the Allwinner H6 main pin controller

The Allwinner H6 SoC has two pin controllers, one main controller
(called CPUX-PORT in user manual) and one controller in CPUs po

pinctrl: sunxi: add support for the Allwinner H6 main pin controller

The Allwinner H6 SoC has two pin controllers, one main controller
(called CPUX-PORT in user manual) and one controller in CPUs power
domain (called CPUS-PORT in user manual).

This commit introduces support for the main pin controller on H6.

The pin bank A and B are not wired out and hidden from the SoC's
documents, however it's shown that the "ATE" (an AC200 chip
co-packaged with the H6 die) is connected to the main SoC die via these
pin banks. The information about these banks is just copied from the BSP
pinctrl driver, but re-formatted to fit the mainline pinctrl driver
format. The GPIO functions are dropped, as they're impossible to use --
except a GPIO&IRQ only pin (PB20) which might be the IRQ of ATE.

Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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License cleanup: add SPDX GPL-2.0 license identifier to files with no license

Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine

License cleanup: add SPDX GPL-2.0 license identifier to files with no license

Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.

By default all files without license information are under the default
license of the kernel, which is GPL version 2.

Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.

This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.

How this work was done:

Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,

Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.

The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.

The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.

Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).

All documentation files were explicitly excluded.

The following heuristics were used to determine which SPDX license
identifiers to apply.

- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.

For non */uapi/* files that summary was:

SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139

and resulted in the first patch in this series.

If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:

SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930

and resulted in the second patch in this series.

- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:

SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1

and that resulted in the third patch in this series.

- when the two scanners agreed on the detected license(s), that became
the concluded license(s).

- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.

- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).

- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.

- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.

In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.

Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.

Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.

In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.

Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct

This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.

These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.

Reviewed-by: Kate Stewart <[email protected]>
Reviewed-by: Philippe Ombredanne <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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pinctrl: sunxi: Add support for A83T R_PIO

The R_PIO on the A83T is almost the same as the one found on the A64,
except that the CIR_RX function was moved from pin PL11 to pin PL12.

Add a driver fo

pinctrl: sunxi: Add support for A83T R_PIO

The R_PIO on the A83T is almost the same as the one found on the A64,
except that the CIR_RX function was moved from pin PL11 to pin PL12.

Add a driver for it.

Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: drop dedicated A20 driver

As we added A20 support to A10 pinctrl driver, now we can delete the
dedicated A20 pinctrl driver, which is duplicated code.

Signed-off-by: Icenowy Zheng <

pinctrl: sunxi: drop dedicated A20 driver

As we added A20 support to A10 pinctrl driver, now we can delete the
dedicated A20 pinctrl driver, which is duplicated code.

Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
[Drop Makefile entry]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add A64 R_PIO controller support

The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
Add support for the pins controlled by the R_PIO controller.

Signed-off-

pinctrl: sunxi: Add A64 R_PIO controller support

The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
Add support for the pins controlled by the R_PIO controller.

Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Remove redundant A31s pinctrl driver

Now that we can support the A31s pin controller with the A31 driver
using the new variants support, the independent A31s driver becomes
redundant

pinctrl: sunxi: Remove redundant A31s pinctrl driver

Now that we can support the A31s pin controller with the A31 driver
using the new variants support, the independent A31s driver becomes
redundant.

Remove it.

Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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drivers: pinctrl: add driver for Allwinner H5 SoC

Based on the Allwinner H5 datasheet and the pinctrl driver of the
backward-compatible H3 this introduces the pin multiplex assignments for
the H5 So

drivers: pinctrl: add driver for Allwinner H5 SoC

Based on the Allwinner H5 datasheet and the pinctrl driver of the
backward-compatible H3 this introduces the pin multiplex assignments for
the H5 SoC.

H5 introduced some more pin functions (e.g. three more groups of TS
pins, and one more groups of SIM pins) than H3.

Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: add driver for V3s SoC

V3s SoC features only a pin controller (for the lack of CPUs part).

Add a driver for this controller.

Signed-off-by: Icenowy Zheng <[email protected]>
Acked-b

pinctrl: sunxi: add driver for V3s SoC

V3s SoC features only a pin controller (for the lack of CPUs part).

Add a driver for this controller.

Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Remove old sun5i pinctrl drivers

Now that we have a common pinctrl driver for all the sun5i SoCs, we can
remove the old, separate drivers.

Signed-off-by: Maxime Ripard <maxime.ripar

pinctrl: sunxi: Remove old sun5i pinctrl drivers

Now that we have a common pinctrl driver for all the sun5i SoCs, we can
remove the old, separate drivers.

Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add common sun5i pinctrl driver

The sun5i SoCs (A10s, A13, GR8) are all based on the same die fit in
different packages. Hence, the pins and functions available are just the
based on

pinctrl: sunxi: Add common sun5i pinctrl driver

The sun5i SoCs (A10s, A13, GR8) are all based on the same die fit in
different packages. Hence, the pins and functions available are just the
based on the same set, each SoC having a different subset.

Introduce a common pinctrl driver that supports multiple variants to allow
to put as much as we can in common.

Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add GR8 controller support

Just like the other member of the sunxi family, let's add a pinctrl table
for the muxing options.

Signed-off-by: Mylène Josserand <mylene.josserand@free-e

pinctrl: sunxi: Add GR8 controller support

Just like the other member of the sunxi family, let's add a pinctrl table
for the muxing options.

Signed-off-by: Mylène Josserand <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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drivers: pinctrl: add driver for Allwinner A64 SoC

Based on the Allwinner A64 user manual and on the previous sunxi
pinctrl drivers this introduces the pin multiplex assignments for
the ARMv8 Allwin

drivers: pinctrl: add driver for Allwinner A64 SoC

Based on the Allwinner A64 user manual and on the previous sunxi
pinctrl drivers this introduces the pin multiplex assignments for
the ARMv8 Allwinner A64 SoC.
Port A is apparently used for the fixed function DRAM controller, so
the ports start at B here (the manual mentions "n from 1 to 7", so
not starting at 0).

Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Rob Herring <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add H3 R_PIO controller support

H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.

Signed-off

pinctrl: sunxi: Add H3 R_PIO controller support

H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.

Signed-off-by: Krzysztof Adamski <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: guard sub-directory with CONFIG_PINCTRL_SUNXI

CONFIG_PINCTRL_SUNXI is more suitable than CONFIG_ARCH_SUNXI
to guard the drivers/pinctrl/sunxi/ directory.
(I renamed CONFIG_PINCTRL_SU

pinctrl: sunxi: guard sub-directory with CONFIG_PINCTRL_SUNXI

CONFIG_PINCTRL_SUNXI is more suitable than CONFIG_ARCH_SUNXI
to guard the drivers/pinctrl/sunxi/ directory.
(I renamed CONFIG_PINCTRL_SUNXI_COMMON to CONFIG_PINCTRL_SUNXI.)

Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add A80 special pin controller

Like the previous designs, the A80 has a special pin controller for the
critical pins, like the PMIC bus.

Add a driver for this controller.

Signed-of

pinctrl: sunxi: Add A80 special pin controller

Like the previous designs, the A80 has a special pin controller for the
critical pins, like the PMIC bus.

Add a driver for this controller.

Signed-off-by: Maxime Ripard <[email protected]>
[wens: Add A80 compatible strings to bindings doc; fix pin function
names based on v1.3 datasheet; constify of_device_id table]
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add H3 PIO controller support

The H3 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.

Signed-off-by: Je

pinctrl: sunxi: Add H3 PIO controller support

The H3 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.

Signed-off-by: Jens Kuske <[email protected]>
Acked-by: Rob Herring <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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