pinctrl: sunxi: Add support for the secondary A523 GPIO ports

As most other Allwinner SoCs before, the A523 chip contains a second
GPIO controller, managing banks PL and PM.
Use the newly introduced

pinctrl: sunxi: Add support for the secondary A523 GPIO ports

As most other Allwinner SoCs before, the A523 chip contains a second
GPIO controller, managing banks PL and PM.
Use the newly introduced DT based pinctrl driver to describe just the
generic pinctrl properties, so advertise the number of pins per bank
and the interrupt capabilities. The actual function/mux assignment is
taken from the devicetree.

Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add support for the Allwinner A523

The Allwinner A523 contains pins in 10 out of the 11 possible pin banks;
it just skips port A.
Use the newly introduced DT based pinctrl driver to

pinctrl: sunxi: Add support for the Allwinner A523

The Allwinner A523 contains pins in 10 out of the 11 possible pin banks;
it just skips port A.
Use the newly introduced DT based pinctrl driver to describe just the
generic pinctrl properties, so advertise the number of pins per bank
and the interrupt capabilities. The actual function/mux assignment is
taken from the devicetree.

Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add driver for Allwinner D1

This SoC contains a pinctrl with a new register layout. Use the variant
parameter to set the right register offsets. This pinctrl also increases
the numbe

pinctrl: sunxi: Add driver for Allwinner D1

This SoC contains a pinctrl with a new register layout. Use the variant
parameter to set the right register offsets. This pinctrl also increases
the number of functions per pin from 8 to 16, taking advantage of all 4
bits in the mux config field (so far, only functions 0-8 and 14-15 are
used). This increases the maximum possible number of functions.

Reviewed-by: Heiko Stuebner <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Remove reset controller consumers

None of the sunxi pin controllers have a module reset line. All of the
SoC documentation, where available, agrees. The bits that would be used
for t

pinctrl: sunxi: Remove reset controller consumers

None of the sunxi pin controllers have a module reset line. All of the
SoC documentation, where available, agrees. The bits that would be used
for the PIO reset (i.e. matching the order of the clock gate bits) are
always reserved, both in the CCU and in the PRCM. And experiments on
several SoCs, including the A33, confirm that those reserved bits indeed
have no effect.

Let's remove this superfluous code and dependency, and also remove the
include statement that was copied to the other r_pio drivers.

Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add support for the Allwinner H616-R pin controller

There are only two pins left now, used to connect to the PMIC via I2C.

Signed-off-by: Andre Przywara <[email protected]>
Ack

pinctrl: sunxi: Add support for the Allwinner H616-R pin controller

There are only two pins left now, used to connect to the PMIC via I2C.

Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add support for the Allwinner H616 pin controller

Port A is used for an internal connection to some analogue circuitry
which looks like an AC200 IP (as in the H6), though this is not

pinctrl: sunxi: Add support for the Allwinner H616 pin controller

Port A is used for an internal connection to some analogue circuitry
which looks like an AC200 IP (as in the H6), though this is not
mentioned in the manual.

Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: add support for the Allwinner A100 pin controller

This commit introduces support for the pin controller on A100.

Signed-off-by: Yangtao Li <[email protected]>
Acked-by: Maxime

pinctrl: sunxi: add support for the Allwinner A100 pin controller

This commit introduces support for the pin controller on A100.

Signed-off-by: Yangtao Li <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Link: https://lore.kernel.org/r/4e331a2ed4a30c883df6157bc5c52bb686aa8e0d.1595572867.git.frank@allwinnertech.com
Signed-off-by: Linus Walleij <[email protected]>

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treewide: Add SPDX license identifier - Makefile/Kconfig

Add SPDX license identifiers to all Make/Kconfig files which:

- Have no license information of any form

These files fall under the project

treewide: Add SPDX license identifier - Makefile/Kconfig

Add SPDX license identifiers to all Make/Kconfig files which:

- Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

GPL-2.0-only

Signed-off-by: Thomas Gleixner <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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pinctrl: sunxi: Allow to disable pinctrl drivers

Our pinctrl drivers are consisting of some common code, and big pin tables
that are SoC-specific. This is fine in most cases, but when you want to
re

pinctrl: sunxi: Allow to disable pinctrl drivers

Our pinctrl drivers are consisting of some common code, and big pin tables
that are SoC-specific. This is fine in most cases, but when you want to
reduce the size of the particular kernel image, those big tables are, well,
quite big.

We haven't had the option to disable them in the past since they were
hidden Kconfig options based on the SoC support. However, that granularity
isn't great since we don't have one Kconfig option per-SoC, but rather one
by family.

Make those options selectable by the user so that they can disable it if
needed, while keeping the current default to not change the standard case.

Acked-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)

The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a
pin
controller like other SoCs from Allwinner.

Add support

pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)

The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a
pin
controller like other SoCs from Allwinner.

Add support for it.

Signed-off-by: Mesih Kilinc <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: add support for H6 R_PIO pin controller

Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs,
which controls the PL and PM pin banks.

Add support for it.

Signed-of

pinctrl: sunxi: add support for H6 R_PIO pin controller

Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs,
which controls the PL and PM pin banks.

Add support for it.

Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: add support for the Allwinner H6 main pin controller

The Allwinner H6 SoC has two pin controllers, one main controller
(called CPUX-PORT in user manual) and one controller in CPUs po

pinctrl: sunxi: add support for the Allwinner H6 main pin controller

The Allwinner H6 SoC has two pin controllers, one main controller
(called CPUX-PORT in user manual) and one controller in CPUs power
domain (called CPUS-PORT in user manual).

This commit introduces support for the main pin controller on H6.

The pin bank A and B are not wired out and hidden from the SoC's
documents, however it's shown that the "ATE" (an AC200 chip
co-packaged with the H6 die) is connected to the main SoC die via these
pin banks. The information about these banks is just copied from the BSP
pinctrl driver, but re-formatted to fit the mainline pinctrl driver
format. The GPIO functions are dropped, as they're impossible to use --
except a GPIO&IRQ only pin (PB20) which might be the IRQ of ATE.

Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: add support of R40 to A10 pinctrl driver

R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).

Add support for R40 to the

pinctrl: sunxi: add support of R40 to A10 pinctrl driver

R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).

Add support for R40 to the A10 pinctrl driver.

Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add support for A83T R_PIO

The R_PIO on the A83T is almost the same as the one found on the A64,
except that the CIR_RX function was moved from pin PL11 to pin PL12.

Add a driver fo

pinctrl: sunxi: Add support for A83T R_PIO

The R_PIO on the A83T is almost the same as the one found on the A64,
except that the CIR_RX function was moved from pin PL11 to pin PL12.

Add a driver for it.

Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: drop dedicated A20 driver

As we added A20 support to A10 pinctrl driver, now we can delete the
dedicated A20 pinctrl driver, which is duplicated code.

Signed-off-by: Icenowy Zheng <

pinctrl: sunxi: drop dedicated A20 driver

As we added A20 support to A10 pinctrl driver, now we can delete the
dedicated A20 pinctrl driver, which is duplicated code.

Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
[Drop Makefile entry]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: add A20 support to A10 driver

As A20 is designed as a pin-compatible upgrade of A10, their pin
controller are very similar, and can share one driver.

Add A20 support to the A10 driv

pinctrl: sunxi: add A20 support to A10 driver

As A20 is designed as a pin-compatible upgrade of A10, their pin
controller are very similar, and can share one driver.

Add A20 support to the A10 driver.

Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: select GPIOLIB

Allwinner pin controllers are also GPIO controllers.

Currently, if GPIOLIB is forgot to be chosen, the build of
pinctrl-sunxi.c will fail for lacking a lot of gpiochi

pinctrl: sunxi: select GPIOLIB

Allwinner pin controllers are also GPIO controllers.

Currently, if GPIOLIB is forgot to be chosen, the build of
pinctrl-sunxi.c will fail for lacking a lot of gpiochip_* functions.

Select GPIOLIB to ensure this driver can be built.

Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add A64 R_PIO controller support

The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
Add support for the pins controlled by the R_PIO controller.

Signed-off-

pinctrl: sunxi: Add A64 R_PIO controller support

The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
Add support for the pins controlled by the R_PIO controller.

Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: refactor pinctrl choice selecting for ARM64

ARM64 Allwinner SoCs used to have every pinctrl driver selected in
ARCH_SUNXI. Change this to make their default value to (ARM64 &&
ARCH_S

pinctrl: sunxi: refactor pinctrl choice selecting for ARM64

ARM64 Allwinner SoCs used to have every pinctrl driver selected in
ARCH_SUNXI. Change this to make their default value to (ARM64 &&
ARCH_SUNXI).

Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Remove redundant A31s pinctrl driver

Now that we can support the A31s pin controller with the A31 driver
using the new variants support, the independent A31s driver becomes
redundant

pinctrl: sunxi: Remove redundant A31s pinctrl driver

Now that we can support the A31s pin controller with the A31 driver
using the new variants support, the independent A31s driver becomes
redundant.

Remove it.

Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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drivers: pinctrl: add driver for Allwinner H5 SoC

Based on the Allwinner H5 datasheet and the pinctrl driver of the
backward-compatible H3 this introduces the pin multiplex assignments for
the H5 So

drivers: pinctrl: add driver for Allwinner H5 SoC

Based on the Allwinner H5 datasheet and the pinctrl driver of the
backward-compatible H3 this introduces the pin multiplex assignments for
the H5 SoC.

H5 introduced some more pin functions (e.g. three more groups of TS
pins, and one more groups of SIM pins) than H3.

Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: add driver for V3s SoC

V3s SoC features only a pin controller (for the lack of CPUs part).

Add a driver for this controller.

Signed-off-by: Icenowy Zheng <[email protected]>
Acked-b

pinctrl: sunxi: add driver for V3s SoC

V3s SoC features only a pin controller (for the lack of CPUs part).

Add a driver for this controller.

Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Remove old sun5i pinctrl drivers

Now that we have a common pinctrl driver for all the sun5i SoCs, we can
remove the old, separate drivers.

Signed-off-by: Maxime Ripard <maxime.ripar

pinctrl: sunxi: Remove old sun5i pinctrl drivers

Now that we have a common pinctrl driver for all the sun5i SoCs, we can
remove the old, separate drivers.

Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add common sun5i pinctrl driver

The sun5i SoCs (A10s, A13, GR8) are all based on the same die fit in
different packages. Hence, the pins and functions available are just the
based on

pinctrl: sunxi: Add common sun5i pinctrl driver

The sun5i SoCs (A10s, A13, GR8) are all based on the same die fit in
different packages. Hence, the pins and functions available are just the
based on the same set, each SoC having a different subset.

Introduce a common pinctrl driver that supports multiple variants to allow
to put as much as we can in common.

Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: sunxi: Add GR8 controller support

Just like the other member of the sunxi family, let's add a pinctrl table
for the muxing options.

Signed-off-by: Mylène Josserand <mylene.josserand@free-e

pinctrl: sunxi: Add GR8 controller support

Just like the other member of the sunxi family, let's add a pinctrl table
for the muxing options.

Signed-off-by: Mylène Josserand <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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