pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC

Add pinctrl driver support for RZ/G3E SoC.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <geert+renesas@gl

pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC

Add pinctrl driver support for RZ/G3E SoC.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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pinctrl: renesas: Select PINCTRL_RZG2L for RZ/V2H(P) SoC

Add explicit selection of the PINCTRL_RZG2L config option for the
RZ/V2H(P) (R9A09G057) SoC, ensuring pin control driver is enabled
for this

pinctrl: renesas: Select PINCTRL_RZG2L for RZ/V2H(P) SoC

Add explicit selection of the PINCTRL_RZG2L config option for the
RZ/V2H(P) (R9A09G057) SoC, ensuring pin control driver is enabled
for this SoC.

Fixes: 9bd95ac86e70 ("pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC")
Reported-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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pinctrl: renesas: rzg2l: Select GPIOLIB_IRQCHIP and IRQ_DOMAIN_HIERARCHY

The pinctrl-rzg2l driver accesses gpio_chip.irq, which is available only
if CONFIG_GPIOLIB_IRQCHIP=y, and uses APIs that are

pinctrl: renesas: rzg2l: Select GPIOLIB_IRQCHIP and IRQ_DOMAIN_HIERARCHY

The pinctrl-rzg2l driver accesses gpio_chip.irq, which is available only
if CONFIG_GPIOLIB_IRQCHIP=y, and uses APIs that are defined only if
CONFIG_IRQ_DOMAIN_HIERARCHY=y (irq_chip_*_parent() APIs).

On ARCH_RZG2L, CONFIG_IRQ_DOMAIN_HIERARCHY is selected anyway, e.g. by
CONFIG_ARM_GIC_V3, but CONFIG_GPIOLIB_IRQCHIP is not (it is on R-Car).
Make this explicit at the driver level for a clearer view of the
dependencies.

Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[geert: select GPIOLIB_IRQCHIP, too]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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pinctrl: renesas: Initial R8A779H0 (R-Car V4M) PFC support

Add initial pin control support for the R-Car V4M (R8A779H0) SoC,
including bias, drive strength and voltage control.

Signed-off-by: Cong

pinctrl: renesas: Initial R8A779H0 (R-Car V4M) PFC support

Add initial pin control support for the R-Car V4M (R8A779H0) SoC,
including bias, drive strength and voltage control.

Signed-off-by: Cong Dang <[email protected]>
[geert: Fixes and cleanups]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/5f59263e75be713dc954007cfeb2c99274c9d761.1706264667.git.geert+renesas@glider.be

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pinctrl: renesas: rzn1: Enable missing PINMUX

Enable pin muxing (eg. programmable function), so that the RZ/N1 GPIO
pins will be configured as specified by the pinmux in the DTS.

This used to be en

pinctrl: renesas: rzn1: Enable missing PINMUX

Enable pin muxing (eg. programmable function), so that the RZ/N1 GPIO
pins will be configured as specified by the pinmux in the DTS.

This used to be enabled implicitly via CONFIG_GENERIC_PINMUX_FUNCTIONS,
however that was removed, since the RZ/N1 driver does not call any of
the generic pinmux functions.

Fixes: 1308fb4e4eae14e6 ("pinctrl: rzn1: Do not select GENERIC_PIN{CTRL_GROUPS,MUX_FUNCTIONS}")
Signed-off-by: Ralph Siemsen <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: renesas: Remove R-Car H3 ES1.* handling

R-Car H3 ES1.* was only available to an internal development group and
needed a lot of quirks and workarounds. These become a maintenance
burden now

pinctrl: renesas: Remove R-Car H3 ES1.* handling

R-Car H3 ES1.* was only available to an internal development group and
needed a lot of quirks and workarounds. These become a maintenance
burden now, so our development group decided to remove upstream support
and disable booting for this SoC. Public users only have ES2 onwards.

Signed-off-by: Wolfram Sang <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support

This patch adds initial pinctrl support for the R-Car V4H (R8A779G0)
SoC, including bias, drive strength and voltage control.

This patch w

pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support

This patch adds initial pinctrl support for the R-Car V4H (R8A779G0)
SoC, including bias, drive strength and voltage control.

This patch was created based on the Rev.0.51 datasheet.

Signed-off-by: LUU HOAI <[email protected]>
Signed-off-by: Takeshi Kihara <[email protected]>
[Morimoto: merge Kihara-san's MODSEL8 fixup patch, cleanup white space, care about reserved bits on each configs, fixup comments, etc.]
Signed-off-by: Kuninori Morimoto <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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pinctrl: renesas: Add RZ/V2M pin and gpio controller driver

Add support for pin and gpio controller driver for RZ/V2M SoC.
Based on the RZ/G2L driver.

Note that the DETDO and DETMS dedicated pins a

pinctrl: renesas: Add RZ/V2M pin and gpio controller driver

Add support for pin and gpio controller driver for RZ/V2M SoC.
Based on the RZ/G2L driver.

Note that the DETDO and DETMS dedicated pins are currently not
documented in the HW manual as to which pin group they are in.
HW team has since said that the output level of 1.8V I/O group 4
(for MD0-7, and debugger) is the same as the 1.8V I/O group 3.

Signed-off-by: Phil Edworthy <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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pinctrl: renesas: Select PINCTRL_RZG2L if ARCH_RZG2L is enabled

GPIO (PINCTRL) block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L
SoC's, so instead of selecting PINCTRL_RZG2L config for each S

pinctrl: renesas: Select PINCTRL_RZG2L if ARCH_RZG2L is enabled

GPIO (PINCTRL) block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L
SoC's, so instead of selecting PINCTRL_RZG2L config for each SoC select
PINCTRL_RZG2L config option if ARCH_RZG2L is enabled. The ARCH_RZG2L
config option is already selected by ARCH_R9A07G043, ARCH_R9A07G044 and
ARCH_R9A07G054.

Signed-off-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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pinctrl: renesas: rzg2l: Add RZ/G2UL support

RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin
definitions are different compared to RZ/G2L.

This patch adds a new compatible to take ca

pinctrl: renesas: rzg2l: Add RZ/G2UL support

RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin
definitions are different compared to RZ/G2L.

This patch adds a new compatible to take care of these differences by
adding r9a07g043_data with r9a07g043_gpio_configs and
rzg2l_dedicated_pins.common.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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pinctrl: renesas: Initial R8A779F0 PFC support

Add initial Pin Function Controller (PFC) support for the Renesas R-Car
S4-8 (R8A779F0) SoC, including bias, drive strength and voltage control.

Based

pinctrl: renesas: Initial R8A779F0 PFC support

Add initial Pin Function Controller (PFC) support for the Renesas R-Car
S4-8 (R8A779F0) SoC, including bias, drive strength and voltage control.

Based on a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/fd8201da404b7b0897130b254380ffc97f437266.1645457792.git.geert+renesas@glider.be

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pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is enabled

RZ/V2L uses the RZ/G2L GPIO and pinctrl driver.
Enable the RZ/G2L pinctrl driver if RZ/V2L is enabled.
Update the description

pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is enabled

RZ/V2L uses the RZ/G2L GPIO and pinctrl driver.
Enable the RZ/G2L pinctrl driver if RZ/V2L is enabled.
Update the description for RZ/V2L pin control support.

Signed-off-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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pinctrl: renesas: Add RZ/G2L pin and gpio controller driver

Add support for pin and gpio controller driver for RZ/G2L SoC.

Based on a patch in the BSP by Hien Huynh <[email protected]>.

Si

pinctrl: renesas: Add RZ/G2L pin and gpio controller driver

Add support for pin and gpio controller driver for RZ/G2L SoC.

Based on a patch in the BSP by Hien Huynh <[email protected]>.

Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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pinctrl: renesas: Initial R8A779A0 (V3U) PFC support

This patch adds initial pinctrl support for the R8A779A0 (V3U) SoC,
including bias, drive strength and voltage control.

Based on patch by LUU HO

pinctrl: renesas: Initial R8A779A0 (V3U) PFC support

This patch adds initial pinctrl support for the R8A779A0 (V3U) SoC,
including bias, drive strength and voltage control.

Based on patch by LUU HOAI <[email protected]>.

Signed-off-by: Ulrich Hecht <[email protected]>
Tested-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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pinctrl: renesas: Reintroduce SH_PFC for common sh-pfc code

Most, but not all, Renesas pin control drivers use the "sh-pfc" pin
control framework. As of commit 8449bfa9e6a9f7ec ("pinctrl: sh-pfc:
C

pinctrl: renesas: Reintroduce SH_PFC for common sh-pfc code

Most, but not all, Renesas pin control drivers use the "sh-pfc" pin
control framework. As of commit 8449bfa9e6a9f7ec ("pinctrl: sh-pfc:
Collect Renesas related CONFIGs in one place"), the code for this
framework is always built when Renesas SoC pin control support is
enabled, regardless of whether the enabled pin control drivers need it
or not.

Fix this by reintroducing the CONFIG_SH_PFC symbol to control inclusion
of the "sh-pfc" framework and its dependencies, and selecting it when
needed.

This reduces kernel size of a typical RZ/A1 or RZ/A2 kernel by more than
6 resp. 11 KiB.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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pinctrl: Rename sh-pfc to renesas

The drivers/pinctrl/sh-pfc subdirectory was originally created to group
pin control drivers for various Renesas SuperH and SH-Mobile platforms.
However, the name "s

pinctrl: Rename sh-pfc to renesas

The drivers/pinctrl/sh-pfc subdirectory was originally created to group
pin control drivers for various Renesas SuperH and SH-Mobile platforms.
However, the name "sh-pfc" no longer reflects its contents, as the
directory now contains pin control drivers for Renesas SuperH, ARM32,
and ARM64 SoCs.

Hence rename the subdirectory from drivers/pinctrl/sh-pfc to
drivers/pinctrl/renesas, and the related Kconfig symbol from
PINCTRL_SH_PFC to PINCTRL_RENESAS.

Rename the git branch in MAINTAINERS, too, for consistency.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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