pinctrl: mvebu: pinctrl driver for 98DX2530 SoC

This pinctrl driver supports the 98DX25xx and 98DX35xx family of chips
from Marvell. It is based on the Marvell SDK with additions for various
(non-gp

pinctrl: mvebu: pinctrl driver for 98DX2530 SoC

This pinctrl driver supports the 98DX25xx and 98DX35xx family of chips
from Marvell. It is based on the Marvell SDK with additions for various
(non-gpio) pin configurations based on the datasheet.

Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: Fix Kconfig indentation

Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
$ sed -e 's/^ /\t/' -i */Kconfig

Signed-off-by: Krzysztof

pinctrl: Fix Kconfig indentation

Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
$ sed -e 's/^ /\t/' -i */Kconfig

Signed-off-by: Krzysztof Kozlowski <[email protected]>

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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treewide: Add SPDX license identifier - Makefile/Kconfig

Add SPDX license identifiers to all Make/Kconfig files which:

- Have no license information of any form

These files fall under the project

treewide: Add SPDX license identifier - Makefile/Kconfig

Add SPDX license identifiers to all Make/Kconfig files which:

- Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

GPL-2.0-only

Signed-off-by: Thomas Gleixner <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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pinctrl: mvebu: add driver for Armada CP110 pinctrl

This commit adds a pinctrl driver for the CP110 part of the Marvell
Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all
the

pinctrl: mvebu: add driver for Armada CP110 pinctrl

This commit adds a pinctrl driver for the CP110 part of the Marvell
Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all
the MPP pins are available. On the other side, the Armada 8K has two
CP110, and the available MPPs are split between the master CP110 (MPPs 32
to 62) and the slave CP110 (MPPs 0 to 31).

The register interface to control the MPPs is however the same as all
other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic.

Signed-off-by: Hanna Hawa <[email protected]>
Reviewed-by: Shadi Ammouri <[email protected]>

[updated for mvebu pinctrl and 4.9 changes:
- converted to simple_mmio
- converted to syscon/regmap
- removed unimplemented .remove function
- dropped DTS changes
- defered gpio ranges to DT
- fixed warning
- properly set soc->nmodes
-- rmk]
Signed-off-by: Russell King <[email protected]>

[ add missing MPP[61:56] function 14 (SDIO)
-- Konstantin Porotchkin]
Signed-off-by: Konstantin Porotchkin <[email protected]>

[ allow to properly register more then one instance of this driver
-- Grzegorz Jaszczyk]
Signed-off-by: Grzegorz Jaszczyk <[email protected]>

[ - rebased on 4.12-rc1
- fixed the 80 character limit for mvebu_mpp_mode array
- aligned the compatible name on the ones already used
- fixed the MPP table for CP110: some MPP are not available on Armada 7K
-- Gregory CLEMENT]
Signed-off-by: Gregory CLEMENT <[email protected]>

Tested-by: Thomas Petazzoni <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: mvebu: add driver for Armada AP806 pinctrl

This commit adds a pinctrl driver for the pin-muxing controller found in
the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register
interfa

pinctrl: mvebu: add driver for Armada AP806 pinctrl

This commit adds a pinctrl driver for the pin-muxing controller found in
the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register
interface is compatible with the one used by previous mvebu pin
controllers, so the common logic in drivers/pinctrl/mvebu/pinctrl-mvebu.c
is used.

Signed-off-by: Hanna Hawa <[email protected]>
Reviewed-by: Shadi Ammouri <[email protected]>
[updated for mvebu pinctrl changes
- converted to simple_mmio
- removed unimplemented .remove function
- removed DTS description
- converted to use syscon/regmap
--rmk]
Signed-off-by: Russell King <[email protected]>
Reviewed-by: Thomas Petazzoni <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: avoid PLAT_ORION dependency

Armada 8040 also needs orion pinctrl, and as these symbols are only
selected, there's no need to make them depend on PLAT_ORION.

Reviewed-by: Thomas Petazzoni <

pinctrl: avoid PLAT_ORION dependency

Armada 8040 also needs orion pinctrl, and as these symbols are only
selected, there's no need to make them depend on PLAT_ORION.

Reviewed-by: Thomas Petazzoni <[email protected]>
Signed-off-by: Russell King <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: armada-37xx: Add pin controller support for Armada 37xx

The Armada 37xx SoC come with 2 pin controllers: one on the south
bridge (managing 28 pins) and one on the north bridge (managing 36

pinctrl: armada-37xx: Add pin controller support for Armada 37xx

The Armada 37xx SoC come with 2 pin controllers: one on the south
bridge (managing 28 pins) and one on the north bridge (managing 36 pins).

At the hardware level the controller configure the pins by group and not
pin by pin. This constraint is reflected in the design of the driver:
only the group related functions are implemented.

Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x

This commit adds a new pinctrl driver for the Marvell Armada 39x
family of processors, which hooks into the existing infrastructure to
suppo

pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x

This commit adds a new pinctrl driver for the Marvell Armada 39x
family of processors, which hooks into the existing infrastructure to
support pin-muxing on Marvell EBU processors. Two variants of the
Armada 39x are supported: 88F6920 (Armada 390) and 88F6928 (Armada
398), which have a few differences in the available functions for
certain pins.

Signed-off-by: Thomas Petazzoni <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: mvebu: new driver for Orion platforms

This commit extends the pinctrl mvebu logic with a new driver to cover
Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281
variants o

pinctrl: mvebu: new driver for Orion platforms

This commit extends the pinctrl mvebu logic with a new driver to cover
Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281
variants of Orion5x, which are the three ones supported by the old
style MPP code in arch/arm/mach-orion5x/.

Signed-off-by: Thomas Petazzoni <[email protected]>
Acked-by: Sebastian Hesselbarth <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: mvebu: dove: request syscon regmap for global registers

Dove pinctrl uses some global config registers to control pins.
This patch requests a syscon regmap for those registers. As this
chan

pinctrl: mvebu: dove: request syscon regmap for global registers

Dove pinctrl uses some global config registers to control pins.
This patch requests a syscon regmap for those registers. As this
changes DT to driver requirements, fallback to a self-registered
regmap with hardcoded resources, if the corresponding syscon DT
node is missing. Also, WARN about old DT binding usage to encourage
users to update their DTBs.

Signed-off-by: Sebastian Hesselbarth <[email protected]>
Acked-by: Linus Walleij <[email protected]>

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pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385

The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of p

pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385

The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.

Signed-off-by: Thomas Petazzoni <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>

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pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375

The Marvell Armada 375 is a new ARM SoC from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxin

pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375

The Marvell Armada 375 is a new ARM SoC from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.

Signed-off-by: Thomas Petazzoni <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
Reviewed-by: Gregory CLEMENT <[email protected]>

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pinctrl: mvebu: move to its own directory

Like the spear platform, the mvebu platform has multiple files: one
core file, and then one file per SoC family. More files will be added
later, as support

pinctrl: mvebu: move to its own directory

Like the spear platform, the mvebu platform has multiple files: one
core file, and then one file per SoC family. More files will be added
later, as support for mach-orion5x and mach-mv78xx0 SoCs is added to
pinctrl-mvebu. For those reasons, having a separate subdirectory,
drivers/pinctrl/mvebu/ makes sense, and it had already been suggested
by Linus Wallej when the driver was originally submitted.

Signed-off-by: Thomas Petazzoni <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>

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