pinctrl: amd: isp411: Add amdisp GPIO pinctrl

Add pinctrl driver support for AMD SoC with isp41 hw ip block.

Signed-off-by: Pratap Nirujogi <[email protected]>
Link: https://lore.kernel.org/2

pinctrl: amd: isp411: Add amdisp GPIO pinctrl

Add pinctrl driver support for AMD SoC with isp41 hw ip block.

Signed-off-by: Pratap Nirujogi <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: spacemit: add support for SpacemiT K1 SoC

SpacemiT's K1 SoC has a pinctrl controller which use single register
to describe all functions, which include bias pull up/down(strong pull),
drive

pinctrl: spacemit: add support for SpacemiT K1 SoC

SpacemiT's K1 SoC has a pinctrl controller which use single register
to describe all functions, which include bias pull up/down(strong pull),
drive strength, schmitter trigger, slew rate, mux mode.

Signed-off-by: Yixun Lan <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: canaan: Add support for k230 SoC

Configuration of the K230 is similar to that of the K210. However, in
K210, the 256 functions for each pin are shared, whereas in K230,
multiplex functions

pinctrl: canaan: Add support for k230 SoC

Configuration of the K230 is similar to that of the K210. However, in
K210, the 256 functions for each pin are shared, whereas in K230,
multiplex functions are different for every pin.

`drv_data` of `pinctrl_pin_desc` is pointing to currently activated
group, which is used to print the name of current function of pin in
`pin_dbg_show` and will be updated in `set_mux`, so they are not set
const.

Signed-off-by: Ze Huang <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: Add driver for the T-Head TH1520 SoC

Add pinctrl driver for the T-Head TH1520 RISC-V SoC.

Tested-by: Thomas Bonnefille <[email protected]>
Signed-off-by: Emil Renner Berthing <

pinctrl: Add driver for the T-Head TH1520 SoC

Add pinctrl driver for the T-Head TH1520 RISC-V SoC.

Tested-by: Thomas Bonnefille <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
[dfustini: use thead,pad-group to identify the pin controller instance]
Signed-off-by: Drew Fustini <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: add a Cirrus ep93xx SoC pin controller

Add a pin control (only multiplexing) driver for ep93xx SoC so
we can fully convert ep93xx to device tree.

This driver is capable of muxing ep9301/ep

pinctrl: add a Cirrus ep93xx SoC pin controller

Add a pin control (only multiplexing) driver for ep93xx SoC so
we can fully convert ep93xx to device tree.

This driver is capable of muxing ep9301/ep9302/ep9307/ep9312/ep9315
variants, this is chosen based on "compatible" in device tree.

Co-developed-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Nikita Shubin <[email protected]>
Tested-by: Alexander Sverdlin <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Acked-by: Vinod Koul <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>

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pinctrl: sophgo: add support for CV1800B SoC

Sophgo CV1800 series SoCs share common control logic but have
different register mapping. For maintenance, split the driver
and pin definition of the SoC

pinctrl: sophgo: add support for CV1800B SoC

Sophgo CV1800 series SoCs share common control logic but have
different register mapping. For maintenance, split the driver
and pin definition of the SoC.

Add base driver for CV1800 series SoC and pin definition of
CV1800B.

Signed-off-by: Inochi Amaoto <[email protected]>
Link: https://lore.kernel.org/IA1PR20MB4953B260E04EC53F6A01EB30BBB32@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: eyeq5: add platform driver

Add the Mobileye EyeQ5 pin controller driver. It belongs to a syscon
region called OLB and gets spawned as auxiliary device to the platform
driver for clock.

Exi

pinctrl: eyeq5: add platform driver

Add the Mobileye EyeQ5 pin controller driver. It belongs to a syscon
region called OLB and gets spawned as auxiliary device to the platform
driver for clock.

Existing pins and their function live statically in the driver code
rather than in the devicetree, see compatible match data.

Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Théo Lebrun <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: Implementation of the generic scmi-pinctrl driver

scmi-pinctrl driver implements pinctrl driver interface and using
SCMI protocol to redirect messages from pinctrl subsystem SDK to
SCMI pla

pinctrl: Implementation of the generic scmi-pinctrl driver

scmi-pinctrl driver implements pinctrl driver interface and using
SCMI protocol to redirect messages from pinctrl subsystem SDK to
SCMI platform firmware, which does the changes in HW.

Co-developed-by: Oleksii Moisieiev <[email protected]>
Signed-off-by: Oleksii Moisieiev <[email protected]>
Reviewed-by: Dhruva Gole <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Sudeep Holla <[email protected]>

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pinctrl: Add driver for Awinic AW9523/B I2C GPIO Expander

The Awinic AW9523(B) is a multi-function I2C gpio expander in a
TQFN-24L package, featuring PWM (max 37mA per pin, or total max
power 3.2Wat

pinctrl: Add driver for Awinic AW9523/B I2C GPIO Expander

The Awinic AW9523(B) is a multi-function I2C gpio expander in a
TQFN-24L package, featuring PWM (max 37mA per pin, or total max
power 3.2Watts) for LED driving capability.

It has two ports with 8 pins per port (for a total of 16 pins),
configurable as either PWM with 1/256 stepping or GPIO input/output,
1.8V logic input; each GPIO can be configured as input or output
independently from each other.

This IC also has an internal interrupt controller, which is capable
of generating an interrupt for each GPIO, depending on the
configuration, and will raise an interrupt on the INTN pin to
advertise this to an external interrupt controller.

Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: David Bauer <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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pinctrl: Add support for the Lantic PEF2256 pinmux

The Lantiq PEF2256 is a framer and line interface component designed to
fulfill all required interfacing between an analog E1/T1/J1 line and the
di

pinctrl: Add support for the Lantic PEF2256 pinmux

The Lantiq PEF2256 is a framer and line interface component designed to
fulfill all required interfacing between an analog E1/T1/J1 line and the
digital PCM system highway/H.100 bus.

This kind of component can be found in old telecommunication system.
It was used to digital transmission of many simultaneous telephone calls
by time-division multiplexing. Also using HDLC protocol, WAN networks
can be reached through the framer.

This pinmux support handles the pin muxing part (pins RP(A..D) and pins
XP(A..D)) of the PEF2256.

Signed-off-by: Herve Codina <[email protected]>
Reviewed-by: Christophe Leroy <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: tps6594: Add driver for TPS6594 pinctrl and GPIOs

TI TPS6594 PMIC has 11 GPIOs which can be used
for different functions.

This patch adds a pinctrl and GPIO drivers in
order to use those f

pinctrl: tps6594: Add driver for TPS6594 pinctrl and GPIOs

TI TPS6594 PMIC has 11 GPIOs which can be used
for different functions.

This patch adds a pinctrl and GPIO drivers in
order to use those functions.

Signed-off-by: Esteban Blanc <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: realtek: Add common pinctrl driver for Realtek DHC RTD SoCs

The RTD SoCs share a similar design for pinmux and pinconfig.
This common pinctrl driver supports different variants within the R

pinctrl: realtek: Add common pinctrl driver for Realtek DHC RTD SoCs

The RTD SoCs share a similar design for pinmux and pinconfig.
This common pinctrl driver supports different variants within the RTD
SoCs.

Signed-off-by: Tzuyi Chang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: pinctrl-oxnas: remove obsolete pinctrl driver

Due to lack of maintenance and stall of development for a few years now,
and since no new features will ever be added upstream, remove support

pinctrl: pinctrl-oxnas: remove obsolete pinctrl driver

Due to lack of maintenance and stall of development for a few years now,
and since no new features will ever be added upstream, remove support
for OX810 and OX820 pinctrl & gpio.

Acked-by: Linus Walleij <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Daniel Golle <[email protected]>
Acked-by: Andy Shevchenko <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/20230814-topic-oxnas-upstream-remove-v3-1-04a0c5cdda52@linaro.org
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: qcom: allow true compile testing

Makefile selected Qualcomm pinctrl drivers only for ARCH_QCOM, making
any COMPILE_TEST options inside Kconfig ((ARCH_QCOM || COMPILE_TEST) or
(OF || COMPILE

pinctrl: qcom: allow true compile testing

Makefile selected Qualcomm pinctrl drivers only for ARCH_QCOM, making
any COMPILE_TEST options inside Kconfig ((ARCH_QCOM || COMPILE_TEST) or
(OF || COMPILE_TEST)) not effective. Always descent to the qcom
subdirectory to fix this. All individual drivers are selected in
Makefile via dedicated CONFIG entries, thus this should not have
functional impact except when compile testing.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: Remove Intel Thunder Bay pinctrl driver

Remove Thunder Bay specific code as the product got cancelled
and there are no end customers or users.

Signed-off-by: Lakshmi Sowjanya D <lakshmi.so

pinctrl: Remove Intel Thunder Bay pinctrl driver

Remove Thunder Bay specific code as the product got cancelled
and there are no end customers or users.

Signed-off-by: Lakshmi Sowjanya D <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: mlxbf3: Add pinctrl driver support

NVIDIA BlueField-3 SoC has a few pins that can be used as GPIOs
or take the default hardware functionality. Add a driver for
the pin muxing.

Signed-off-b

pinctrl: mlxbf3: Add pinctrl driver support

NVIDIA BlueField-3 SoC has a few pins that can be used as GPIOs
or take the default hardware functionality. Add a driver for
the pin muxing.

Signed-off-by: Asmaa Mnebhi <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: ralink: move to mediatek as mtmips

This platform from Ralink was acquired by MediaTek in 2011. Then, MediaTek
introduced new SoCs which utilise this platform. Move the driver to
mediatek pi

pinctrl: ralink: move to mediatek as mtmips

This platform from Ralink was acquired by MediaTek in 2011. Then, MediaTek
introduced new SoCs which utilise this platform. Move the driver to
mediatek pinctrl directory. Rename the ralink core driver to mtmips.

Signed-off-by: Arınç ÜNAL <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: add NXP S32 SoC family support

Add the pinctrl driver for NXP S32 SoC family. This driver is mainly based
on NXP's downstream implementation on nxp-auto-linux repo[1].

[1] https://github.c

pinctrl: add NXP S32 SoC family support

Add the pinctrl driver for NXP S32 SoC family. This driver is mainly based
on NXP's downstream implementation on nxp-auto-linux repo[1].

[1] https://github.com/nxp-auto-linux/linux/tree/bsp35.0-5.15.73-rt/drivers/pinctrl/freescale

Signed-off-by: Matthew Nunez <[email protected]>
Signed-off-by: Phu Luu An <[email protected]>
Signed-off-by: Stefan-Gabriel Mirea <[email protected]>
Signed-off-by: Larisa Grigore <[email protected]>
Signed-off-by: Ghennadi Procopciuc <[email protected]>
Signed-off-by: Andrei Stefanescu <[email protected]>
Signed-off-by: Radu Pirea <[email protected]>
Signed-off-by: Chester Lin <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: pinctrl-loongson2: add pinctrl driver support

The Loongson-2 SoC has a few pins that can be used as GPIOs or take
multiple other functions. Add a driver for the pinmuxing.

There is current

pinctrl: pinctrl-loongson2: add pinctrl driver support

The Loongson-2 SoC has a few pins that can be used as GPIOs or take
multiple other functions. Add a driver for the pinmuxing.

There is currently no support for GPIO pin pull-up and pull-down.

Signed-off-by: zhanghongchen <[email protected]>
Co-developed-by: Yinbo Zhu <[email protected]>
Signed-off-by: Yinbo Zhu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: Create subdirectory for StarFive drivers

Move the StarFive JH7100 pinctrl driver to a new subdirectory
in preparation for adding more StarFive pinctrl drivers. No
functional change.

Signed

pinctrl: Create subdirectory for StarFive drivers

Move the StarFive JH7100 pinctrl driver to a new subdirectory
in preparation for adding more StarFive pinctrl drivers. No
functional change.

Signed-off-by: Jianlong Huang <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: Add Cypress cy8c95x0 support

Add support for cypress I2C GPIO expanders cy8c9520, cy8c9540 and
cy8c9560. The GPIO expanders feature a PWM mode, thus add it as
pinctrl driver.

The chip feat

pinctrl: Add Cypress cy8c95x0 support

Add support for cypress I2C GPIO expanders cy8c9520, cy8c9540 and
cy8c9560. The GPIO expanders feature a PWM mode, thus add it as
pinctrl driver.

The chip features multiple drive modes for each pin when configured
as output and multiple bias settings when configured as input.

Tested all three components and verified that all functionality
is fully working.

Datasheet: https://www.cypress.com/file/37971/download
Signed-off-by: Patrick Rudolph <[email protected]>
Signed-off-by: Naresh Solanki <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: nuvoton: Add driver for WPCM450

This driver is based on the one for NPCM7xx, because the WPCM450 is a
predecessor of those SoCs. Notable differences:

- On WPCM450, the GPIO registers are n

pinctrl: nuvoton: Add driver for WPCM450

This driver is based on the one for NPCM7xx, because the WPCM450 is a
predecessor of those SoCs. Notable differences:

- On WPCM450, the GPIO registers are not organized in multiple banks,
but rather placed continually into the same register block. This
affects how register offsets are computed.
- Pinmux nodes can explicitly select GPIO mode, whereas in the npcm7xx
driver, this happens automatically when a GPIO is requested.

Some functionality implemented in the hardware was (for now) left unused
in the driver, specifically blinking and pull-up/down.

Signed-off-by: Jonathan Neuschäfer <[email protected]>
Reported-by: kernel test robot <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: Add driver for Sunplus SP7021

Add driver for Sunplus SP7021 SoC.

Signed-off-by: Wells Lu <[email protected]>
Link: https://lore.kernel.org/r/1642344734-27229-3-git-send-email-wellslutw@g

pinctrl: Add driver for Sunplus SP7021

Add driver for Sunplus SP7021 SoC.

Signed-off-by: Wells Lu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>

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pinctrl: Place correctly CONFIG_PINCTRL_ST in the Makefile

Keep Makefile entries ordered in the same way as Kconfig ones.

Reported-by: Linus Torvalds <[email protected]>
Signed-off-by:

pinctrl: Place correctly CONFIG_PINCTRL_ST in the Makefile

Keep Makefile entries ordered in the same way as Kconfig ones.

Reported-by: Linus Torvalds <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>

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pinctrl: starfive: Add pinctrl driver for StarFive SoCs

Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which
is

pinctrl: starfive: Add pinctrl driver for StarFive SoCs

Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which
is said to feature only minor changes to these pinctrl/GPIO parts.

For each "GPIO" there are two registers for configuring the output and
output enable signals which may come from other peripherals. Among these
are two special signals that are constant 0 and constant 1 respectively.
Controlling the GPIOs from software is done by choosing one of these
signals. In other words the same registers are used for both pin muxing
and controlling the GPIOs, which makes it easier to combine the pinctrl
and GPIO driver in one.

I wrote the pinconf and pinmux parts, but the GPIO part of the code is
based on the GPIO driver in the vendor tree written by Huan Feng with
cleanups and fixes by Drew and me.

Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
Reviewed-by: Andy Shevchenko <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Co-developed-by: Huan Feng <[email protected]>
Signed-off-by: Huan Feng <[email protected]>
Co-developed-by: Drew Fustini <[email protected]>
Signed-off-by: Drew Fustini <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

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