phy: ti: fix Kconfig warning and operator precedence

Fix Kconfig depends operator precedence to prevent a Kconfig warning:

WARNING: unmet direct dependencies detected for MUX_MMIO
Depends on [n]:

phy: ti: fix Kconfig warning and operator precedence

Fix Kconfig depends operator precedence to prevent a Kconfig warning:

WARNING: unmet direct dependencies detected for MUX_MMIO
Depends on [n]: MULTIPLEXER [=m] && OF [=n]
Selected by [m]:
- PHY_AM654_SERDES [=m] && (OF [=n] && ARCH_K3 || COMPILE_TEST [=y]) && COMMON_CLK [=y]

Fixes: 71e2f5c5c224 ("phy: ti: Add a new SERDES driver for TI's AM654x SoC")
Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Signed-off-by: Randy Dunlap <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: [email protected]
Cc: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>

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phy: ti: gmii-sel: simplify config dependencies between net drivers and gmii phy

The phy-gmii-sel can be only auto selected in Kconfig and now the pretty
complex Kconfig dependencies are defined for

phy: ti: gmii-sel: simplify config dependencies between net drivers and gmii phy

The phy-gmii-sel can be only auto selected in Kconfig and now the pretty
complex Kconfig dependencies are defined for phy-gmii-sel driver, which
also need to be updated every time phy-gmii-sel is re-used for any new
networking driver.

Simplify Kconfig definition for phy-gmii-sel PHY driver - drop all
dependencies and from networking drivers and rely on using 'imply
PHY_TI_GMII_SEL' in Kconfig definitions for networking drivers instead.

Signed-off-by: Grygorii Strashko <[email protected]>
Acked-by: Kishon Vijay Abraham I <[email protected]>
Tested-by: Murali Karicheri <[email protected]>
Tested-by: Peter Ujfalusi <[email protected]>
Signed-off-by: David S. Miller <[email protected]>

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phy: ti: j721e-wiz: Fix build error without CONFIG_OF_ADDRESS

If CONFIG_OF_ADDRESS is not set and COMPILE_TEST=y, the following
error is seen while building phy-j721e-wiz.c

drivers/phy/ti/phy-j721e

phy: ti: j721e-wiz: Fix build error without CONFIG_OF_ADDRESS

If CONFIG_OF_ADDRESS is not set and COMPILE_TEST=y, the following
error is seen while building phy-j721e-wiz.c

drivers/phy/ti/phy-j721e-wiz.o: In function `wiz_remove':
phy-j721e-wiz.c:(.text+0x1a): undefined reference to
`of_platform_device_destroy'

Fix the config dependency for PHY_J721E_WIZ here.

Reported-by: Hulk Robot <[email protected]>
Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Signed-off-by: Hongbo Yao <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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phy: Enable compile testing for some of drivers

Some of the phy drivers can be compile tested to increase build
coverage.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Florian Fain

phy: Enable compile testing for some of drivers

Some of the phy drivers can be compile tested to increase build
coverage.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>

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phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC

Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to th

phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC

Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to the SERDES. It is
used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures
three clock selects (pll0, pll1, dig), two divider clocks and supports
resets for each of the lanes.

[[email protected]: Add support for Torrent(10G) SERDES wrapper]
Signed-off-by: Jyri Sarha <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>

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phy: Enable compile testing for some of drivers

Some of the phy drivers can be compile tested to increase build
coverage.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.ker

phy: Enable compile testing for some of drivers

Some of the phy drivers can be compile tested to increase build
coverage.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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phy: ti: phy-gmii-sel: dependency from ti cpsw-switchdev driver

Add dependency from TI_CPSW_SWITCHDEV.

Signed-off-by: Grygorii Strashko <[email protected]>
Signed-off-by: David S. Miller <da

phy: ti: phy-gmii-sel: dependency from ti cpsw-switchdev driver

Add dependency from TI_CPSW_SWITCHDEV.

Signed-off-by: Grygorii Strashko <[email protected]>
Signed-off-by: David S. Miller <[email protected]>

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treewide: Add SPDX license identifier - Makefile/Kconfig

Add SPDX license identifiers to all Make/Kconfig files which:

- Have no license information of any form

These files fall under the project

treewide: Add SPDX license identifier - Makefile/Kconfig

Add SPDX license identifiers to all Make/Kconfig files which:

- Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

GPL-2.0-only

Signed-off-by: Thomas Gleixner <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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phy: ti: Add a new SERDES driver for TI's AM654x SoC

Add a new SERDES driver for TI's AM654x SoC which configures
the SERDES only for PCIe. Support fo USB3 will be added later.

SERDES in am654x has

phy: ti: Add a new SERDES driver for TI's AM654x SoC

Add a new SERDES driver for TI's AM654x SoC which configures
the SERDES only for PCIe. Support fo USB3 will be added later.

SERDES in am654x has three input clocks (left input, externel reference
clock and right input) and two output clocks (left output and right
output) in addition to a PLL mux clock which the SERDES uses for Clock
Multiplier Unit (CMU refclock).

The PLL mux clock can select from one of the three input clocks.
The right output can select between left input and external reference
clock while the left output can select between the right input and
external reference clock.

The driver has support to select PLL mux and left/right output mux as
specified in device tree.

[[email protected]: Fix boot lockup caused by accessing a structure member
(hw->init) allocated in stack of probe() and accessed in get_parent]
[[email protected]: Fix "Failed to find the parent" warnings]
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>

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phy: ti: usb2: fix OMAP_CONTROL_PHY dependency

With randconfig build testing on arm64, we can run into a configuration
that has CONFIG_OMAP_CONTROL_PHY=m and CONFIG_OMAP_USB2=y, which in turn
causes

phy: ti: usb2: fix OMAP_CONTROL_PHY dependency

With randconfig build testing on arm64, we can run into a configuration
that has CONFIG_OMAP_CONTROL_PHY=m and CONFIG_OMAP_USB2=y, which in turn
causes a link failure:

drivers/phy/ti/phy-omap-usb2.o: In function `omap_usb_phy_power':
phy-omap-usb2.c:(.text+0x17c): undefined reference to `omap_control_phy_power'

I could not come up with a good way to correctly describe the relation
of the two symbols, but if we just select CONFIG_OMAP_CONTROL_PHY
during compile testing, we can no longer run into the broken configuration.

Fixes: 6777cee3a872 ("phy: ti: usb2: Add support for AM654 USB2 PHY")
Signed-off-by: Arnd Bergmann <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>

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phy: ti: usb2: Add support for AM654 USB2 PHY

Add support for the USB2 PHY on the AM654 SoC.

Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Sekhar Nori <[email protected]>
Signed-off-by:

phy: ti: usb2: Add support for AM654 USB2 PHY

Add support for the USB2 PHY on the AM654 SoC.

Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Sekhar Nori <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>

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phy: ti: Don't depend on OMAP_OCP2SCP

TI_PIPE3 and OMAP_USB2 don't depend on OMAP_OCP2SCP
for build.

Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Sekhar Nori <[email protected]>
Signed-

phy: ti: Don't depend on OMAP_OCP2SCP

TI_PIPE3 and OMAP_USB2 don't depend on OMAP_OCP2SCP
for build.

Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Sekhar Nori <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>

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phy: ti: Fix compilation failures without REGMAP

This driver requires regmap or the compile fails:

drivers/phy/ti/phy-gmii-sel.c:43:27: error: array type has incomplete element type ‘struct reg_fie

phy: ti: Fix compilation failures without REGMAP

This driver requires regmap or the compile fails:

drivers/phy/ti/phy-gmii-sel.c:43:27: error: array type has incomplete element type ‘struct reg_field’
const struct reg_field (*regfields)[PHY_GMII_SEL_LAST];

Add it to kconfig.

Signed-off-by: Jason Gunthorpe <[email protected]>
Signed-off-by: David S. Miller <[email protected]>

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phy: ti: introduce phy-gmii-sel driver

TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports two
10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII
interfaces. The inte

phy: ti: introduce phy-gmii-sel driver

TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports two
10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII
interfaces. The interface mode is selected by configuring the MII mode
selection register(s) (GMII_SEL) in the System Control Module chapter
(SCM). GMII_SEL register(s) and bit fields placement in SCM are different
between SoCs while fields meaning is the same.

Historically CPSW external Port's interface mode selection configuration
was introduced using custom API and driver cpsw-phy-sel.c. This leads to
unnecessary driver, DT binding and custom API support effort.

This patch introduces CPSW Port's PHY Interface Mode selection Driver
(phy-gmii-sel) which implements standard Linux PHY interface and used
as a replacement for TI's specific driver cpsw-phy-sel.c and corresponding
custom API.

Cc: Kishon Vijay Abraham I <[email protected]>
Cc: Tony Lindgren <[email protected]>
Signed-off-by: Grygorii Strashko <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>

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phy: Group vendor specific phy drivers

Adding vendor specific directories in phy to group
phy drivers under their respective vendor umbrella.

Also updated the MAINTAINERS file to reflect the correc

phy: Group vendor specific phy drivers

Adding vendor specific directories in phy to group
phy drivers under their respective vendor umbrella.

Also updated the MAINTAINERS file to reflect the correct
directory structure for phy drivers.

Signed-off-by: Vivek Gautam <[email protected]>
Acked-by: Heiko Stuebner <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Yoshihiro Shimoda <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Geert Uytterhoeven <[email protected]>
Cc: Yoshihiro Shimoda <[email protected]>
Cc: Guenter Roeck <[email protected]>
Cc: Heiko Stuebner <[email protected]>
Cc: Viresh Kumar <[email protected]>
Cc: Maxime Ripard <[email protected]>
Cc: Chen-Yu Tsai <[email protected]>
Cc: Sylwester Nawrocki <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Martin Blumenstingl <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>

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