| c8879d3f | 27-Feb-2023 |
Michael Grzeschik <[email protected]> |
phy: stm32-usphyc: add 200 to 300 us delay to fix timeout on some machines
An minimum udelay of 200 us seems to be necessary on some machines. After
the setup of the pll, which needs about 100 us to
phy: stm32-usphyc: add 200 to 300 us delay to fix timeout on some machines
An minimum udelay of 200 us seems to be necessary on some machines. After
the setup of the pll, which needs about 100 us to be locked there seem
to be additional 100 us to get the phy really functional. Without this
delay the usb runs not functional. With this additional short udelay
this issue was not reported again.
Signed-off-by: Michael Grzeschik <[email protected]>
Reviewed-by: Fabrice Gasnier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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| 2f5e9f81 | 15-Oct-2021 |
Amelie Delaunay <[email protected]> |
phy: stm32: add phy tuning support
It can be necessary to adjust the phys settings to compensate parasitics.
This patch adds support of new optional properties to configure the tune
interface of the
phy: stm32: add phy tuning support
It can be necessary to adjust the phys settings to compensate parasitics.
This patch adds support of new optional properties to configure the tune
interface of the phys of stm32-usbphyc.
Properties are optional, that's why each property is skipped if not
found (-EINVAL).
Phy tuning is restored on resume because if deep low power state is
achieved, phy tuning configuration is reset.
Signed-off-by: Amelie Delaunay <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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| 5b1af712 | 05-Jan-2021 |
Amelie Delaunay <[email protected]> |
phy: stm32: rework PLL Lock detection
USBPHYC has a register per phy to control and monitor the debug interface
of the HS PHY through a digital debug access.
With this register, it is possible to kn
phy: stm32: rework PLL Lock detection
USBPHYC has a register per phy to control and monitor the debug interface
of the HS PHY through a digital debug access.
With this register, it is possible to know if PLL Lock input to phy is
high. That means the PLL is ready for HS operation.
Instead of using an hard-coded delay after PLL enable and PLL disable, use
this bit to ensure good operating of the HS PHY.
Also use an atomic counter (n_pll_cons) to count the actual number of PLL
consumers and get rid of stm32_usbphyc_has_one_phy_active.
The boolean active in the usbphyc_phy structure is kept, because we need to
know in remove if a phy_exit is required to properly disable the PLL.
Signed-off-by: Amelie Delaunay <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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| 64962724 | 05-Jan-2021 |
Amelie Delaunay <[email protected]> |
phy: stm32: ensure phy are no more active when removing the driver
To ensure a good balancing of regulators, and allow PLL disabling when the
driver is removed, call stm32_usbphyc_phy_exit on each p
phy: stm32: ensure phy are no more active when removing the driver
To ensure a good balancing of regulators, and allow PLL disabling when the
driver is removed, call stm32_usbphyc_phy_exit on each ports to set phys
inactive and disable PLL.
Signed-off-by: Amelie Delaunay <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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