| aecb63e8 | 05-Mar-2025 |
Stefan Eichenberger <[email protected]> |
phy: freescale: imx8m-pcie: assert phy reset and perst in power off
Ensure the PHY reset and perst is asserted during power-off to
guarantee it is in a reset state upon repeated power-on calls. This
phy: freescale: imx8m-pcie: assert phy reset and perst in power off
Ensure the PHY reset and perst is asserted during power-off to
guarantee it is in a reset state upon repeated power-on calls. This
resolves an issue where the PHY may not properly initialize during
subsequent power-on cycles. Power-on will deassert the reset at the
appropriate time after tuning the PHY parameters.
During suspend/resume cycles, we observed that the PHY PLL failed to
lock during resume when the CPU temperature increased from 65C to 75C.
The observed errors were:
phy phy-32f00000.pcie-phy.3: phy poweron failed --> -110
imx6q-pcie 33800000.pcie: waiting for PHY ready timeout!
imx6q-pcie 33800000.pcie: PM: dpm_run_callback(): genpd_resume_noirq+0x0/0x80 returns -110
imx6q-pcie 33800000.pcie: PM: failed to resume noirq: error -110
This resulted in a complete CPU freeze, which is resolved by ensuring
the PHY is in reset during power-on, thus preventing PHY PLL failures.
Cc: [email protected]
Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver")
Signed-off-by: Stefan Eichenberger <[email protected]>
Reviewed-by: Frank Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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| 97e8a2ff | 05-Mar-2025 |
Stefan Eichenberger <[email protected]> |
phy: freescale: imx8m-pcie: cleanup reset logic
Remove the switch statement and base perst release on whether it is
found in the device tree. The probe function fails without the reset
property, mak
phy: freescale: imx8m-pcie: cleanup reset logic
Remove the switch statement and base perst release on whether it is
found in the device tree. The probe function fails without the reset
property, making it mandatory. Therefore, always release reset
independent of the variant.
This does not change the behavior of the driver but reduces driver
complexity and allows for easier future modifications.
Signed-off-by: Stefan Eichenberger <[email protected]>
Reviewed-by: Frank Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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| d567679f | 26-Oct-2024 |
Adam Ford <[email protected]> |
phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation
Currently, the calcuation for fld_tg_code is based on a lookup table,
but there are gaps in the lookup table, and frequencies in th
phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation
Currently, the calcuation for fld_tg_code is based on a lookup table,
but there are gaps in the lookup table, and frequencies in these
gaps may not properly use the correct divider. Based on the description
of FLD_CK_DIV, the internal PLL frequency should be less than 50 MHz,
so directly calcuate the value of FLD_CK_DIV from pixclk.
This allow for proper calcuation of any pixel clock and eliminates a
few gaps in the LUT.
Since the value of the int_pllclk is in Hz, do the fixed-point
math in Hz to achieve a more accurate value and reduces the complexity
of the caluation to 24MHz * (256 / int_pllclk).
Fixes: 6ad082bee902 ("phy: freescale: add Samsung HDMI PHY")
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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| 1b9b8b15 | 26-Oct-2024 |
Adam Ford <[email protected]> |
phy: freescale: fsl-samsung-hdmi: Stop searching when exact match is found
There are a series of for-loops which check various values of P and S
for the integer divder PLL. The for loops search all
phy: freescale: fsl-samsung-hdmi: Stop searching when exact match is found
There are a series of for-loops which check various values of P and S
for the integer divder PLL. The for loops search all entries and use
the one closest to the nominal, but it continues to searches through
all for loops even after the nominal is achieved. Ending when the
nominal value is found stops wasting time, since it will not find
a better value than a deviation of 0 Hz.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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| 75884445 | 14-Sep-2024 |
Adam Ford <[email protected]> |
phy: freescale: fsl-samsung-hdmi: Remove unnecessary LUT entries
The lookup table contains entries which use the integer divider
instead of just the fractional divider. Since the set and round
funct
phy: freescale: fsl-samsung-hdmi: Remove unnecessary LUT entries
The lookup table contains entries which use the integer divider
instead of just the fractional divider. Since the set and round
functions check both the integer divider values and the LUT values,
it's no longer necessary to keep the integer divider values in the
lookup table, as can be dynamically calcuated.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Tested-by: Frieder Schrempf <[email protected]>
Reviewed-by: Dominique Martinet <[email protected]>
Tested-by: Dominique Martinet <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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| 058ea4a0 | 14-Sep-2024 |
Adam Ford <[email protected]> |
phy: freescale: fsl-samsung-hdmi: Use closest divider
Currently, if the clock values cannot be set to the exact rate,
the round_rate and set_rate functions use the closest value found in
the look-up
phy: freescale: fsl-samsung-hdmi: Use closest divider
Currently, if the clock values cannot be set to the exact rate,
the round_rate and set_rate functions use the closest value found in
the look-up-table. In preparation of removing values from the LUT
that can be calculated evenly with the integer calculator, it's
necessary to ensure to check both the look-up-table and the integer
divider clock values to get the closest values to the requested
value. It does this by measuring the difference between the
requested clock value and the closest value in both integer divider
calucator and the fractional clock look-up-table.
Which ever has the smallest difference between them is returned as
the closest rate.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Dominique Martinet <[email protected]>
Tested-by: Dominique Martinet <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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| 1951dbb4 | 14-Sep-2024 |
Adam Ford <[email protected]> |
phy: freescale: fsl-samsung-hdmi: Support dynamic integer
There is currently a look-up table for a variety of resolutions.
Since the phy has the ability to dynamically calculate the values
necessary
phy: freescale: fsl-samsung-hdmi: Support dynamic integer
There is currently a look-up table for a variety of resolutions.
Since the phy has the ability to dynamically calculate the values
necessary to use the intger divider which should allow more
resolutions without having to update the look-up-table.
If the lookup table cannot find an exact match, fall back to the
dynamic calculator of the integer divider.
Previously, the value of P was hard-coded to 1, this required an
update to the phy_pll_cfg table to add in the extra value into the
table, so if the value of P is calculated to be something else
by the PMS calculator, the calculated_phy_pll_cfg structure
can be used instead without having to keep track of which method
was used.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Dominique Martinet <[email protected]>
Tested-by: Dominique Martinet <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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| 375ee44a | 14-Sep-2024 |
Adam Ford <[email protected]> |
phy: freescale: fsl-samsung-hdmi: Simplify REG21_PMS_S_MASK lookup
The value of 'S' is writen to two places, PHY_REG3[7:4] and
PHY_REG21[3:0]. There is a lookup table which contains
the value of PH
phy: freescale: fsl-samsung-hdmi: Simplify REG21_PMS_S_MASK lookup
The value of 'S' is writen to two places, PHY_REG3[7:4] and
PHY_REG21[3:0]. There is a lookup table which contains
the value of PHY_REG3. Rather than using a switch statement
based on the pixel clock to search for the value of 'S' again,
just shift the contents of PHY_REG3[7:4] >> 4 and place the value
in PHY_REG21[3:0]. Doing this can eliminate an entire function.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Tested-by: Frieder Schrempf <[email protected]>
Reviewed-by: Dominique Martinet <[email protected]>
Tested-by: Dominique Martinet <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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| aefa036b | 20-Jun-2024 |
Nathan Chancellor <[email protected]> |
phy: freescale: imx8qm-hsio: Include bitfield.h for FIELD_PREP
In various configurations/architectures, bitfield.h may not be
transitively included, which results in a compiler error because
FIELD_P
phy: freescale: imx8qm-hsio: Include bitfield.h for FIELD_PREP
In various configurations/architectures, bitfield.h may not be
transitively included, which results in a compiler error because
FIELD_PREP is an unexpanded macro:
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c:459:8: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
459 | val = FIELD_PREP(HSIO_MODE_MASK, val);
| ^
1 error generated.
Include bitfield.h explicitly to fix the build.
Fixes: 82c56b6dd24f ("phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support")
Signed-off-by: Nathan Chancellor <[email protected]>
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Reviewed-by: Frank Li <[email protected]>
Link: https://lore.kernel.org/r/20240620-phy-fsl-imx8qm-hsio-add-bitfield-include-v1-1-5c7c09ed87e6@kernel.org
Signed-off-by: Vinod Koul <[email protected]>
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| c49de54c | 09-Apr-2024 |
Uwe Kleine-König <[email protected]> |
phy: freescale: fsl-samsung-hdmi: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's p
phy: freescale: fsl-samsung-hdmi: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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| 139ad114 | 04-Oct-2023 |
Vladimir Oltean <[email protected]> |
phy: lynx-28g: serialize concurrent phy_set_mode_ext() calls to shared registers
The protocol converter configuration registers PCC8, PCCC, PCCD
(implemented by the driver), as well as others, contr
phy: lynx-28g: serialize concurrent phy_set_mode_ext() calls to shared registers
The protocol converter configuration registers PCC8, PCCC, PCCD
(implemented by the driver), as well as others, control protocol
converters from multiple lanes (each represented as a different
struct phy). So, if there are simultaneous calls to phy_set_mode_ext()
to lanes sharing the same PCC register (either for the "old" or for the
"new" protocol), corruption of the values programmed to hardware is
possible, because lynx_28g_rmw() has no locking.
Add a spinlock in the struct lynx_28g_priv shared by all lanes, and take
the global spinlock from the phy_ops :: set_mode() implementation. There
are no other callers which modify PCC registers.
Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G")
Signed-off-by: Vladimir Oltean <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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