| 9651f789 | 17-Mar-2025 |
Robin Murphy <[email protected]> |
perf/arm_cspmu: Fix missing io.h include
Adding the writel() calls needs io.h, which apparently gets
transiently included somewhere on arm64, but not elsewhere.
Fixes: 6de0298a3925 ("perf/arm_cspmu
perf/arm_cspmu: Fix missing io.h include
Adding the writel() calls needs io.h, which apparently gets
transiently included somewhere on arm64, but not elsewhere.
Fixes: 6de0298a3925 ("perf/arm_cspmu: Generalise event filtering")
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Signed-off-by: Robin Murphy <[email protected]>
Link: https://lore.kernel.org/r/657935ca177024ad08d5ec6f85e8faf75f82cf65.1742212833.git.robin.murphy@arm.com
Signed-off-by: Will Deacon <[email protected]>
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| a28f3cbf | 05-Mar-2025 |
Robin Murphy <[email protected]> |
perf/arm_cspmu: Add PMEVFILT2R support
Architecturally we have two filters for each regular event counter,
so add generic support for the second one too.
Signed-off-by: Robin Murphy <robin.murphy@a
perf/arm_cspmu: Add PMEVFILT2R support
Architecturally we have two filters for each regular event counter,
so add generic support for the second one too.
Signed-off-by: Robin Murphy <[email protected]>
Reviewed-by: James Clark <[email protected]>
Reviewed-by: Ilkka Koskinen <[email protected]>
Link: https://lore.kernel.org/r/b11be3f23a72bc27088b115099c8fe865b70babc.1741190362.git.robin.murphy@arm.com
Signed-off-by: Will Deacon <[email protected]>
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| 6de0298a | 05-Mar-2025 |
Robin Murphy <[email protected]> |
perf/arm_cspmu: Generalise event filtering
The notion of a single u32 filter value for any event doesn't scale well
when the potential architectural scope is already two 64-bit values, and
implement
perf/arm_cspmu: Generalise event filtering
The notion of a single u32 filter value for any event doesn't scale well
when the potential architectural scope is already two 64-bit values, and
implementations may add custom stuff on the side too. Rather than try to
thread arbitrary filter data through the common path, let's just make
the set_ev_filter op self-contained in terms of parsing and configuring
any and all filtering for the given event - splitting out a distinct op
for cycles events which inherently differ - and let implementations
override the whole thing if they want to do something different. This
already allows the Ampere code to stop looking a bit hacky.
Signed-off-by: Robin Murphy <[email protected]>
Reviewed-by: James Clark <[email protected]>
Reviewed-by: Ilkka Koskinen <[email protected]>
Link: https://lore.kernel.org/r/c0cd4d4c12566dbf1b062ccd60241b3e0639f4cc.1741190362.git.robin.murphy@arm.com
Signed-off-by: Will Deacon <[email protected]>
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| bce61d5c | 31-Oct-2024 |
Besar Wicaksono <[email protected]> |
perf: arm_cspmu: nvidia: monitor all ports by default
Some NVIDIA PMUs like the NVLINK-C2C, CNVLINK, and PCIE PMU provide
port filtering. If the port filter is set to zero, the counter of
these PMUs
perf: arm_cspmu: nvidia: monitor all ports by default
Some NVIDIA PMUs like the NVLINK-C2C, CNVLINK, and PCIE PMU provide
port filtering. If the port filter is set to zero, the counter of
these PMUs will not capture any event. To avoid meaningless
experiment, the driver sets the port filter value to a default
non-zero value.
Signed-off-by: Besar Wicaksono <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Will Deacon <[email protected]>
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| e7e8fa8e | 06-Feb-2024 |
Robin Murphy <[email protected]> |
perf/arm_cspmu: Simplify counter reset
arm_cspmu_reset_counters() inherently also stops them since it is
writing 0 to PMCR.E, so there should be no need to do that twice.
Also tidy up the reset rout
perf/arm_cspmu: Simplify counter reset
arm_cspmu_reset_counters() inherently also stops them since it is
writing 0 to PMCR.E, so there should be no need to do that twice.
Also tidy up the reset routine itself for consistency with the start
and stop routines, and to be clear at first glance that it is simply
writing a constant value.
Reviewed-by: Ilkka Koskinen <[email protected]>
Signed-off-by: Robin Murphy <[email protected]>
Reviewed-by: Suzuki K Poulose <[email protected]>
Link: https://lore.kernel.org/r/3105815327989f6bb7bb068994d0eb4096b4ef64.1706718007.git.robin.murphy@arm.com
Signed-off-by: Will Deacon <[email protected]>
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| 7e6a3c3f | 06-Feb-2024 |
Robin Murphy <[email protected]> |
perf/arm_cspmu: Simplify attribute groups
The attribute group array itself is always the same, so there's no
need to allocate it separately. Storing it directly in our instance
data saves memory and
perf/arm_cspmu: Simplify attribute groups
The attribute group array itself is always the same, so there's no
need to allocate it separately. Storing it directly in our instance
data saves memory and gives us one less point of failure.
Reviewed-by: Ilkka Koskinen <[email protected]>
Signed-off-by: Robin Murphy <[email protected]>
Reviewed-by: Suzuki K Poulose <[email protected]>
Link: https://lore.kernel.org/r/cf12b803114b0815438833fcb2495f20f2007761.1706718007.git.robin.murphy@arm.com
Signed-off-by: Will Deacon <[email protected]>
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| 647d5c5a | 13-Sep-2023 |
Ilkka Koskinen <[email protected]> |
perf: arm_cspmu: Support implementation specific validation
Some platforms may use e.g. different filtering mechanism and, thus,
may need different way to validate the events and group.
Signed-off-
perf: arm_cspmu: Support implementation specific validation
Some platforms may use e.g. different filtering mechanism and, thus,
may need different way to validate the events and group.
Signed-off-by: Ilkka Koskinen <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Suzuki K Poulose <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Will Deacon <[email protected]>
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| 0a7603ab | 13-Sep-2023 |
Ilkka Koskinen <[email protected]> |
perf: arm_cspmu: Support implementation specific filters
ARM Coresight PMU architecture specification [1] defines PMEVTYPER and
PMEVFILT* registers as optional in Chapter 2.1. Moreover, implementers
perf: arm_cspmu: Support implementation specific filters
ARM Coresight PMU architecture specification [1] defines PMEVTYPER and
PMEVFILT* registers as optional in Chapter 2.1. Moreover, implementers may
choose to use PMIMPDEF* registers (offset: 0xD80-> 0xDFF) to filter the
events. Add support for those by adding implementation specific filter
callback function.
[1] https://developer.arm.com/documentation/ihi0091/latest
Signed-off-by: Ilkka Koskinen <[email protected]>
Reviewed-by: Besar Wicaksono <[email protected]>
Reviewed-by: Suzuki K Poulose <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Will Deacon <[email protected]>
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