| e31e67f5 | 22-Mar-2025 |
Hans-Frieder Vogt <[email protected]> |
net: phy: aquantia: add essential functions to aqr105 driver
This patch makes functions that were provided for aqr107 applicable to
aqr105, or replaces generic functions with specific ones. Since th
net: phy: aquantia: add essential functions to aqr105 driver
This patch makes functions that were provided for aqr107 applicable to
aqr105, or replaces generic functions with specific ones. Since the aqr105
was introduced before NBASE-T was defined (or 802.3bz), there are a number
of vendor specific registers involved in the definition of the
advertisement, in auto-negotiation and in the setting of the speed. The
functions have been written following the downstream driver for TN4010
cards with aqr105 PHY, and use code from aqr107 functions wherever it
seemed to make sense.
Signed-off-by: Hans-Frieder Vogt <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Jakub Kicinski <[email protected]>
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| 7e5b547c | 10-Oct-2024 |
Aryan Srivastava <[email protected]> |
net: phy: aquantia: poll status register
The system interface connection status register is not immediately
correct upon line side link up. This results in the status being read as
OFF and then tran
net: phy: aquantia: poll status register
The system interface connection status register is not immediately
correct upon line side link up. This results in the status being read as
OFF and then transitioning to the correct host side link mode with a
short delay. This causes the phylink framework passing the OFF status
down to all MAC config drivers, resulting in the host side link being
misconfigured, which in turn can lead to link flapping or complete
packet loss in some cases.
Mitigate this by periodically polling the register until it not showing
the OFF state. This will be done every 1ms for 10ms, using the same
poll/timeout as the processor intensive operation reads.
If the phy is still expressing the OFF state after the timeout, then set
the link to false and pass the NA interface mode onto the phylink
framework.
Signed-off-by: Aryan Srivastava <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Jakub Kicinski <[email protected]>
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| 8f61d733 | 01-Oct-2024 |
Abhishek Chauhan <[email protected]> |
net: phy: aquantia: remove usage of phy_set_max_speed
Remove the use of phy_set_max_speed in phy driver as the
function is mainly used in MAC driver to set the max
speed.
Instead use get_features t
net: phy: aquantia: remove usage of phy_set_max_speed
Remove the use of phy_set_max_speed in phy driver as the
function is mainly used in MAC driver to set the max
speed.
Instead use get_features to fix up Phy PMA capabilities for
AQR111, AQR111B0, AQR114C and AQCS109
Fixes: 038ba1dc4e54 ("net: phy: aquantia: add AQR111 and AQR111B0 PHY ID")
Fixes: 0974f1f03b07 ("net: phy: aquantia: remove false 5G and 10G speed ability for AQCS109")
Fixes: c278ec644377 ("net: phy: aquantia: add support for AQR114C PHY ID")
Link: https://lore.kernel.org/all/[email protected]/T/
Signed-off-by: Abhishek Chauhan <[email protected]>
Reviewed-by: Russell King (Oracle) <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Jakub Kicinski <[email protected]>
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| 6f9defaf | 17-Sep-2024 |
Daniel Golle <[email protected]> |
net: phy: aquantia: fix applying active_low bit after reset
for_each_set_bit was used wrongly in aqr107_config_init() when iterating
over LEDs. Drop misleading 'index' variable and call
aqr_phy_led_
net: phy: aquantia: fix applying active_low bit after reset
for_each_set_bit was used wrongly in aqr107_config_init() when iterating
over LEDs. Drop misleading 'index' variable and call
aqr_phy_led_active_low_set() for each set bit representing an LED which
is driven by VDD instead of GND pin.
Fixes: 61578f679378 ("net: phy: aquantia: add support for PHY LEDs")
Signed-off-by: Daniel Golle <[email protected]>
Reviewed-by: Russell King (Oracle) <[email protected]>
Link: https://patch.msgid.link/9b1f0cd91f4cda54c8be56b4fe780480baf4aa0f.1726580902.git.daniel@makrotopia.org
Signed-off-by: Paolo Abeni <[email protected]>
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| 0ebc581f | 08-Jul-2024 |
Bartosz Golaszewski <[email protected]> |
net: phy: aquantia: add support for aqr115c
Add support for a new model to the Aquantia driver. This PHY supports
2.5 gigabit speeds. The PHY mode is referred to by the manufacturer as
Overclocked S
net: phy: aquantia: add support for aqr115c
Add support for a new model to the Aquantia driver. This PHY supports
2.5 gigabit speeds. The PHY mode is referred to by the manufacturer as
Overclocked SGMII (OCSGMII) but this actually is just 2500BASEX without
in-band signalling so reuse the existing mode to avoid changing the
uAPI.
Signed-off-by: Bartosz Golaszewski <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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| 708405f3 | 08-Jul-2024 |
Bartosz Golaszewski <[email protected]> |
net: phy: aquantia: wait for the GLOBAL_CFG to start returning real values
When the PHY is first coming up (or resuming from suspend), it's
possible that although the FW status shows as running, we
net: phy: aquantia: wait for the GLOBAL_CFG to start returning real values
When the PHY is first coming up (or resuming from suspend), it's
possible that although the FW status shows as running, we still see
zeroes in the GLOBAL_CFG set of registers and cannot determine available
modes. Since all models support 10M, add a poll and wait the config to
become available.
Signed-off-by: Bartosz Golaszewski <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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| ad649a1f | 08-Jul-2024 |
Bartosz Golaszewski <[email protected]> |
net: phy: aquantia: wait for FW reset before checking the vendor ID
Checking the firmware register before it complete the boot process makes
no sense, it will report 0 even if FW is available from i
net: phy: aquantia: wait for FW reset before checking the vendor ID
Checking the firmware register before it complete the boot process makes
no sense, it will report 0 even if FW is available from internal memory.
Always wait for FW to boot before continuing or we'll unnecessarily try
to load it from nvmem/filesystem and fail.
Signed-off-by: Bartosz Golaszewski <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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| 61578f67 | 31-May-2024 |
Daniel Golle <[email protected]> |
net: phy: aquantia: add support for PHY LEDs
Aquantia Ethernet PHYs got 3 LED output pins which are typically used
to indicate link status and activity.
Add a minimal LED controller driver supportin
net: phy: aquantia: add support for PHY LEDs
Aquantia Ethernet PHYs got 3 LED output pins which are typically used
to indicate link status and activity.
Add a minimal LED controller driver supporting the most common uses
with the 'netdev' trigger as well as software-driven forced control of
the LEDs.
Signed-off-by: Daniel Golle <[email protected]>
[ rework indentation, fix checkpatch error and improve some functions ]
Signed-off-by: Christian Marangi <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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