| e8d2d287 | 19-Mar-2025 |
Nathan Chancellor <[email protected]> |
i3c: master: svc: Fix implicit fallthrough in svc_i3c_master_ibi_work()
Clang warns (or errors with CONFIG_WERROR=y):
drivers/i3c/master/svc-i3c-master.c:596:2: error: unannotated fall-through be
i3c: master: svc: Fix implicit fallthrough in svc_i3c_master_ibi_work()
Clang warns (or errors with CONFIG_WERROR=y):
drivers/i3c/master/svc-i3c-master.c:596:2: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough]
596 | default:
| ^
drivers/i3c/master/svc-i3c-master.c:596:2: note: insert 'break;' to avoid fall-through
596 | default:
| ^
| break;
1 error generated.
Clang is a little more pedantic than GCC, which does not warn when
falling through to a case that is just break or return. Clang's version
is more in line with the kernel's own stance in deprecated.rst, which
states that all switch/case blocks must end in either break,
fallthrough, continue, goto, or return. Add the missing break to silence
the warning.
Fixes: 0430bf9bc1ac ("i3c: master: svc: Fix missing STOP for master request")
Signed-off-by: Nathan Chancellor <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| c06acf71 | 18-Mar-2025 |
Stanley Chu <[email protected]> |
i3c: master: svc: Use readsb helper for reading MDB
The target can send the MDB byte followed by additional data bytes.
The readl on MRDATAB reads one actual byte, but the readsl advances
the destin
i3c: master: svc: Use readsb helper for reading MDB
The target can send the MDB byte followed by additional data bytes.
The readl on MRDATAB reads one actual byte, but the readsl advances
the destination pointer by 4 bytes. This causes the subsequent payload
to be copied to wrong position in the destination buffer.
Cc: [email protected]
Fixes: dd3c52846d59 ("i3c: master: svc: Add Silvaco I3C master driver")
Signed-off-by: Stanley Chu <[email protected]>
Reviewed-by: Frank Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| 9cecad13 | 18-Mar-2025 |
Stanley Chu <[email protected]> |
i3c: master: svc: Fix missing the IBI rules
The code does not add IBI rules for devices with controller capability.
However, the secondary controller has the controller capability and works
at targe
i3c: master: svc: Fix missing the IBI rules
The code does not add IBI rules for devices with controller capability.
However, the secondary controller has the controller capability and works
at target mode when the device is probed. Therefore, add IBI rules for
such devices.
Fixes: dd3c52846d59 ("i3c: master: svc: Add Silvaco I3C master driver")
Signed-off-by: Stanley Chu <[email protected]>
Reviewed-by: Frank Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| d6cb667b | 10-Mar-2025 |
Stanley Chu <[email protected]> |
i3c: master: svc: Fix i3c_master_get_free_addr return check
The return value of i3c_master_get_free_addr is assigned to a variable
with wrong type, so it can't be negative. Use a signed integer for
i3c: master: svc: Fix i3c_master_get_free_addr return check
The return value of i3c_master_get_free_addr is assigned to a variable
with wrong type, so it can't be negative. Use a signed integer for the
return value. If the value is negative, break the process and propagate
the error code.
This commit also fixes the uninitialized symbol 'dyn_addr', reported
by Smatch static checker.
Fixes: 4008a74e0f9b ("i3c: master: svc: Fix npcm845 FIFO empty issue")
Reported-by: Dan Carpenter <[email protected]>
Closes: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Stanley Chu <[email protected]>
Reviewed-by: Frank Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| 2a785307 | 06-Mar-2025 |
Stanley Chu <[email protected]> |
i3c: master: svc: Fix npcm845 DAA process corruption
When MCONFIG.SKEW=0 and MCONFIG.ODHPP=0, the ENTDAA transaction gets
corrupted and results in a no repeated-start condition at the end of
address
i3c: master: svc: Fix npcm845 DAA process corruption
When MCONFIG.SKEW=0 and MCONFIG.ODHPP=0, the ENTDAA transaction gets
corrupted and results in a no repeated-start condition at the end of
address assignment.
Workaround: Set MCONFIG.SKEW to 1 before initiating the DAA process.
After the DAA process is completed, return MCONFIG.SKEW to its previous
value.
Reviewed-by: Frank Li <[email protected]>
Signed-off-by: Stanley Chu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| 4dd12e94 | 06-Mar-2025 |
Stanley Chu <[email protected]> |
i3c: master: svc: Fix npcm845 invalid slvstart event
I3C HW may generate an invalid SlvStart event when emitting a STOP.
If it is a true SlvStart, the MSTATUS state is SLVREQ. Check the
MSTATUS stat
i3c: master: svc: Fix npcm845 invalid slvstart event
I3C HW may generate an invalid SlvStart event when emitting a STOP.
If it is a true SlvStart, the MSTATUS state is SLVREQ. Check the
MSTATUS state to ignore the false event.
Reviewed-by: Frank Li <[email protected]>
Signed-off-by: Stanley Chu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| 4008a74e | 06-Mar-2025 |
Stanley Chu <[email protected]> |
i3c: master: svc: Fix npcm845 FIFO empty issue
I3C HW stalls the write transfer if the transmit FIFO becomes empty,
when new data is written to FIFO, I3C HW resumes the transfer but the
first transm
i3c: master: svc: Fix npcm845 FIFO empty issue
I3C HW stalls the write transfer if the transmit FIFO becomes empty,
when new data is written to FIFO, I3C HW resumes the transfer but the
first transmitted data bit may have the wrong value.
Fill the FIFO in advance to prevent FIFO from becoming empty.
Reviewed-by: Frank Li <[email protected]>
Signed-off-by: Stanley Chu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| 98d87600 | 06-Mar-2025 |
Stanley Chu <[email protected]> |
i3c: master: svc: Add support for Nuvoton npcm845 i3c
Nuvoton npcm845 SoC uses an older IP version, which has specific
hardware issues that need to be addressed with a different compatible
string.
i3c: master: svc: Add support for Nuvoton npcm845 i3c
Nuvoton npcm845 SoC uses an older IP version, which has specific
hardware issues that need to be addressed with a different compatible
string.
Add driver data for different compatible strings to define platform
specific quirks.
Add compatible string for npcm845 to define its own driver data.
Signed-off-by: Stanley Chu <[email protected]>
Reviewed-by: Frank Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| a892ee4c | 29-Jan-2025 |
Frank Li <[email protected]> |
i3c: master: svc: Flush FIFO before sending Dynamic Address Assignment(DAA)
Ensure the FIFO is empty before issuing the DAA command to prevent
incorrect command data from being sent. Align with othe
i3c: master: svc: Flush FIFO before sending Dynamic Address Assignment(DAA)
Ensure the FIFO is empty before issuing the DAA command to prevent
incorrect command data from being sent. Align with other data transfers,
such as svc_i3c_master_start_xfer_locked(), which flushes the FIFO before
sending a command.
Signed-off-by: Frank Li <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| e55905a3 | 07-Jan-2025 |
Wolfram Sang <[email protected]> |
i3c: mipi-i3c-hci: use parity8 helper instead of open coding it
The kernel has now a generic helper for getting parity with easier to
understand semantics. Make use of it. Here, it also fixes a bug
i3c: mipi-i3c-hci: use parity8 helper instead of open coding it
The kernel has now a generic helper for getting parity with easier to
understand semantics. Make use of it. Here, it also fixes a bug because
the correct algorithm is using XOR ('^=') instead of ADD ('+=').
Signed-off-by: Wolfram Sang <[email protected]>
Tested-by: Jarkko Nikula <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| ccdb2e0e | 31-Dec-2024 |
Jarkko Nikula <[email protected]> |
i3c: mipi-i3c-hci: Add Intel specific quirk to ring resuming
MIPI I3C HCI on Intel hardware requires a quirk where ring needs to stop
and set to run again after resuming the halted controller. This
i3c: mipi-i3c-hci: Add Intel specific quirk to ring resuming
MIPI I3C HCI on Intel hardware requires a quirk where ring needs to stop
and set to run again after resuming the halted controller. This is not
expected from the MIPI I3C HCI specification and is Intel specific.
Add this quirk to generic aborted transfer handling and execute it only
when ring is not in running state after a transfer error and attempted
controller resume. This is the case on Intel hardware.
It is not fully clear to me what is the ring running state in generic
hardware in such case. I would expect if ring is not running, then stop
request is a no-op and run request is either required or does the same
what controller resume would do.
Signed-off-by: Jarkko Nikula <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| 2b50719d | 13-Nov-2024 |
Billy Tsai <[email protected]> |
i3c: mipi-i3c-hci: Support SETDASA CCC
When the I3C subsystem wants to assign a dynamic address using the SETDASA
CCC, it needs to attach the I3C device with device info that includes only
the stati
i3c: mipi-i3c-hci: Support SETDASA CCC
When the I3C subsystem wants to assign a dynamic address using the SETDASA
CCC, it needs to attach the I3C device with device info that includes only
the static address. In the HCI, if the driver want to send this SETDASA
CCC, a DAT entry is required to temporarily fill the device's static
address into the dynamic address field. Afterward, the reattach API will
be executed to update the DAT with the correct dynamic addrees value.
Signed-off-by: Billy Tsai <[email protected]>
Reviewed-by: Jarkko Nikula <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| 473d0cb4 | 14-Nov-2024 |
Shyam Sundar S K <[email protected]> |
i3c: dw: Add quirk to address OD/PP timing issue on AMD platform
The AMD Legacy I3C is having a problem with its IP, specifically with the
push-pull and open-drain pull-up registers. These registers
i3c: dw: Add quirk to address OD/PP timing issue on AMD platform
The AMD Legacy I3C is having a problem with its IP, specifically with the
push-pull and open-drain pull-up registers. These registers need to be
manually programmed for every CCC submission to align with the duty cycle.
Therefore, add a quirk to address this issue.
Reviewed-by: Jarkko Nikula <[email protected]>
Co-developed-by: Sanket Goswami <[email protected]>
Signed-off-by: Sanket Goswami <[email protected]>
Signed-off-by: Shyam Sundar S K <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| 25bc99be | 01-Nov-2024 |
Frank Li <[email protected]> |
i3c: master: svc: Modify enabled_events bit 7:0 to act as IBI enable counter
Fix issue where disabling IBI on one device disables the entire IBI
interrupt. Modify bit 7:0 of enabled_events to serve
i3c: master: svc: Modify enabled_events bit 7:0 to act as IBI enable counter
Fix issue where disabling IBI on one device disables the entire IBI
interrupt. Modify bit 7:0 of enabled_events to serve as an IBI enable
counter, ensuring that the system IBI interrupt is disabled only when all
I3C devices have IBI disabled.
Cc: [email protected]
Fixes: 7ff730ca458e ("i3c: master: svc: enable the interrupt in the enable ibi function")
Reviewed-by: Miquel Raynal <[email protected]>
Signed-off-by: Frank Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| 18599e93 | 30-Sep-2024 |
Jinjie Ruan <[email protected]> |
i3c: master: svc: Fix pm_runtime_set_suspended() with runtime pm enabled
It is not valid to call pm_runtime_set_suspended() for devices
with runtime PM enabled because it returns -EAGAIN if it is en
i3c: master: svc: Fix pm_runtime_set_suspended() with runtime pm enabled
It is not valid to call pm_runtime_set_suspended() for devices
with runtime PM enabled because it returns -EAGAIN if it is enabled
already and working. So, call pm_runtime_disable() before to fix it.
Cc: [email protected] # v5.17
Fixes: 05be23ef78f7 ("i3c: master: svc: add runtime pm support")
Reviewed-by: Frank Li <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Signed-off-by: Jinjie Ruan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|
| 45357c9b | 20-Sep-2024 |
Jarkko Nikula <[email protected]> |
i3c: mipi-i3c-hci: Handle interrupts according to current specifications
Current MIPI I3C HCI specification versions pre-1.0, 1.0. 1.1 and 1.2
don't have cascaded interrupt bits for the PIO and DMA
i3c: mipi-i3c-hci: Handle interrupts according to current specifications
Current MIPI I3C HCI specification versions pre-1.0, 1.0. 1.1 and 1.2
don't have cascaded interrupt bits for the PIO and DMA (ring headers) in
the INTR_STATUS register as implemented currently in the code. Instead
bits 9:0 are marked as reserved with unspecified reset value.
To my understanding they were planned to be introduced in the version 2
and the original commit 9ad9a52cce28 ("i3c/master: introduce the
mipi-i3c-hci driver") was coding ahead according to a draft. With
remarks though.
This is causing that the DMA handler is not called until at least one
reserved bit 7:0 is set in the INTR_STATUS.
Since it looks that idea was dropped in later official versions and to
make able to handle DMA interrupts on an HW that is implemented
according to current specifications call assigned PIO or DMA IO handler
unconditionally.
While doing so remove cascaded interrupt bit definitions and the mask
argument passed to the handler functions.
Signed-off-by: Jarkko Nikula <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
show more ...
|