|
Revision tags: v6.15, v6.15-rc7, v6.15-rc6, v6.15-rc5, v6.15-rc4, v6.15-rc3, v6.15-rc2, v6.15-rc1, v6.14, v6.14-rc7, v6.14-rc6, v6.14-rc5, v6.14-rc4, v6.14-rc3, v6.14-rc2, v6.14-rc1, v6.13, v6.13-rc7, v6.13-rc6, v6.13-rc5, v6.13-rc4, v6.13-rc3, v6.13-rc2, v6.13-rc1, v6.12, v6.12-rc7, v6.12-rc6, v6.12-rc5, v6.12-rc4, v6.12-rc3, v6.12-rc2, v6.12-rc1, v6.11 |
|
| #
71a3161e |
| 13-Sep-2024 |
Maarten Lankhorst <[email protected]> |
drm/xe: Fix DSB buffer coherency
Add the scanout flag to force WC caching, and add the memory barrier where needed.
Reviewed-by: Matthew Auld <[email protected]> Reviewed-by: Ville Syrjälä <vi
drm/xe: Fix DSB buffer coherency
Add the scanout flag to force WC caching, and add the memory barrier where needed.
Reviewed-by: Matthew Auld <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Maarten Lankhorst <[email protected]>
show more ...
|
|
Revision tags: v6.11-rc7, v6.11-rc6 |
|
| #
cad08fa7 |
| 29-Aug-2024 |
Matt Roper <[email protected]> |
drm/xe/display: Drop unnecessary xe_gt.h includes
None of the Xe display files work directly with the GT or need anything from xe_gt.h. Drop the unnecessary include.
Signed-off-by: Matt Roper <mat
drm/xe/display: Drop unnecessary xe_gt.h includes
None of the Xe display files work directly with the GT or need anything from xe_gt.h. Drop the unnecessary include.
Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Himal Prasad Ghimiray <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
show more ...
|
|
Revision tags: v6.11-rc5, v6.11-rc4, v6.11-rc3, v6.11-rc2, v6.11-rc1, v6.10, v6.10-rc7 |
|
| #
27cb2b7f |
| 03-Jul-2024 |
Matthew Auld <[email protected]> |
drm/xe/bmg: implement Wa_16023588340
This involves enabling l2 caching of host side memory access to VRAM through the CPU BAR. The main fallout here is with display since VRAM writes from CPU can no
drm/xe/bmg: implement Wa_16023588340
This involves enabling l2 caching of host side memory access to VRAM through the CPU BAR. The main fallout here is with display since VRAM writes from CPU can now be cached in GPU l2, and display is never coherent with caches, so needs various manual flushing. In the case of fbc we disable it due to complications in getting this to work correctly (in a later patch).
Signed-off-by: Matthew Auld <[email protected]> Cc: Jonathan Cavitt <[email protected]> Cc: Matt Roper <[email protected]> Cc: Lucas De Marchi <[email protected]> Cc: Vinod Govindapillai <[email protected]> Reviewed-by: Jonathan Cavitt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit 01570b446939c3538b1aa3d059837f49fa14a3ae) Signed-off-by: Rodrigo Vivi <[email protected]>
show more ...
|
| #
01570b44 |
| 03-Jul-2024 |
Matthew Auld <[email protected]> |
drm/xe/bmg: implement Wa_16023588340
This involves enabling l2 caching of host side memory access to VRAM through the CPU BAR. The main fallout here is with display since VRAM writes from CPU can no
drm/xe/bmg: implement Wa_16023588340
This involves enabling l2 caching of host side memory access to VRAM through the CPU BAR. The main fallout here is with display since VRAM writes from CPU can now be cached in GPU l2, and display is never coherent with caches, so needs various manual flushing. In the case of fbc we disable it due to complications in getting this to work correctly (in a later patch).
Signed-off-by: Matthew Auld <[email protected]> Cc: Jonathan Cavitt <[email protected]> Cc: Matt Roper <[email protected]> Cc: Lucas De Marchi <[email protected]> Cc: Vinod Govindapillai <[email protected]> Reviewed-by: Jonathan Cavitt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
show more ...
|
|
Revision tags: v6.10-rc6, v6.10-rc5, v6.10-rc4, v6.10-rc3, v6.10-rc2 |
|
| #
8e712bd7 |
| 29-May-2024 |
Jani Nikula <[email protected]> |
drm/xe/display: drop i915_drv.h include from xe code
Drop i915_drv.h include from xe display code as much as possible, and switch to xe types where necessary.
Reviewed-by: Rodrigo Vivi <rodrigo.viv
drm/xe/display: drop i915_drv.h include from xe code
Drop i915_drv.h include from xe display code as much as possible, and switch to xe types where necessary.
Reviewed-by: Rodrigo Vivi <[email protected]> Acked-by: Rodrigo Vivi <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/bb490f3e928fd8178277fde2435de80638fc5715.1717004739.git.jani.nikula@intel.com
show more ...
|
|
Revision tags: v6.10-rc1, v6.9, v6.9-rc7, v6.9-rc6, v6.9-rc5, v6.9-rc4, v6.9-rc3, v6.9-rc2, v6.9-rc1 |
|
| #
62742d12 |
| 22-Mar-2024 |
Lucas De Marchi <[email protected]> |
drm/xe: Normalize bo flags macros
The flags stored in the BO grew over time without following much a naming pattern. First of all, get rid of the _BIT suffix that was banned from everywhere else due
drm/xe: Normalize bo flags macros
The flags stored in the BO grew over time without following much a naming pattern. First of all, get rid of the _BIT suffix that was banned from everywhere else due to the guideline in drivers/gpu/drm/i915/i915_reg.h that xe kind of follows:
Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
Here the flags aren't for a register, but it's good practice to keep it consistent.
Second divergence on names is the use or not of "CREATE". This is because most of the flags are passed to xe_bo_create*() family of functions, changing its behavior. However, since the flags are also stored in the bo itself and checked elsewhere in the code, it seems better to just omit the CREATE part.
With those 2 guidelines, all the flags are given the form XE_BO_FLAG_<FLAG_NAME> with the following commands:
git grep -le "XE_BO_" -- drivers/gpu/drm/xe | xargs sed -i \ -e "s/XE_BO_\([_A-Z0-9]*\)_BIT/XE_BO_\1/g" \ -e 's/XE_BO_CREATE_/XE_BO_FLAG_/g' git grep -le "XE_BO_" -- drivers/gpu/drm/xe | xargs sed -i -r \ -e 's/XE_BO_(DEFER_BACKING|SCANOUT|FIXED_PLACEMENT|PAGETABLE|NEEDS_CPU_ACCESS|NEEDS_UC|INTERNAL_TEST|INTERNAL_64K|GGTT_INVALIDATE)/XE_BO_FLAG_\1/g'
And then the defines in drivers/gpu/drm/xe/xe_bo.h are adjusted to follow the coding style.
Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]>
show more ...
|
|
Revision tags: v6.8, v6.8-rc7, v6.8-rc6, v6.8-rc5, v6.8-rc4, v6.8-rc3, v6.8-rc2, v6.8-rc1, v6.7, v6.7-rc8, v6.7-rc7, v6.7-rc6, v6.7-rc5, v6.7-rc4 |
|
| #
a754391f |
| 01-Dec-2023 |
Animesh Manna <[email protected]> |
drm/xe/dsb: DSB implementation for xe
Add xe specific DSB buffer handling methods.
v1: Initial version. v2: Add null check after dynamic memory allocation of vma. [Uma]
Reviewed-by: Uma Shankar <u
drm/xe/dsb: DSB implementation for xe
Add xe specific DSB buffer handling methods.
v1: Initial version. v2: Add null check after dynamic memory allocation of vma. [Uma]
Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Animesh Manna <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
show more ...
|