| 46e2ffbd | 07-Feb-2025 |
Jani Nikula <[email protected]> |
drm/i915/pch: Remove unused i915->pch_id
With the PCH checks based on PCH types instead of IDs, the i915->pch_id
member has become unused. Remove it.
Reviewed-by: Nemesa Garg <[email protected]
drm/i915/pch: Remove unused i915->pch_id
With the PCH checks based on PCH types instead of IDs, the i915->pch_id
member has become unused. Remove it.
Reviewed-by: Nemesa Garg <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/fac1c59800128e8f398e83d718a3a5dc235d0526.1738923308.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <[email protected]>
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| c2d55e70 | 07-Feb-2025 |
Jani Nikula <[email protected]> |
drm/i915/pch: Hide PCH device IDs
Only the PCH identification code needs the PCH device IDs, as all the
PCH checks are now based on PCH type. Hide the PCH device IDs inside
intel_pch.c. Remove the u
drm/i915/pch: Hide PCH device IDs
Only the PCH identification code needs the PCH device IDs, as all the
PCH checks are now based on PCH type. Hide the PCH device IDs inside
intel_pch.c. Remove the unused INTEL_PCH_ID() macro while at it.
Reviewed-by: Nemesa Garg <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/d1ceb9fc461cf21e1b885a55293f593eba1458ea.1738923308.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <[email protected]>
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| d0a6e501 | 14-Jun-2024 |
Jani Nikula <[email protected]> |
drm/i915: use i9xx_fsb_freq() for GT clock frequency
Reuse i9xx_fsb_freq() for GT clock frequency initialization instead of
depending on rawclk_freq.
Note: If the init order was changed, we could u
drm/i915: use i9xx_fsb_freq() for GT clock frequency
Reuse i9xx_fsb_freq() for GT clock frequency initialization instead of
depending on rawclk_freq.
Note: If the init order was changed, we could use i915->fsb_freq
directly. However, GT clock initialization is done in
i915_driver_mmio_probe(), but intel_dram_detect() later in
i915_driver_hw_probe(), with a dependency on intel_pcode_init().
Reviewed-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/0678d8ec9772725b47d4fa5b14e3b3a34256d5cf.1718356614.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <[email protected]>
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| fc8bf961 | 14-Jun-2024 |
Jani Nikula <[email protected]> |
drm/i915: extend the fsb_freq initialization to more platforms
Initialize fsb frequency for more platforms to be able to use it for GT
clock and rawclk frequency initialization.
Note: There's a dis
drm/i915: extend the fsb_freq initialization to more platforms
Initialize fsb frequency for more platforms to be able to use it for GT
clock and rawclk frequency initialization.
Note: There's a discrepancy between existing pnv_fsb_freq() and
i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
mobile.
Default to 1333 MHz for unknown values, similar to i9xx_hrawclk().
v2:
- Add MISSING_CASE() (Ville)
- Default to the same frequency for both branches (Ville)
Reviewed-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/7cd6dbd4dafb900ac1dd12be0ec096ff1d5fc6cf.1718356614.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <[email protected]>
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| 846bd608 | 14-Jun-2024 |
Jani Nikula <[email protected]> |
drm/i915/dram: rearrange mem freq init
Follow the same style in mem freq init as in fsb freq init, returning
the value instead of assigning in multiple places.
Reviewed-by: Matt Roper <matthew.d.ro
drm/i915/dram: rearrange mem freq init
Follow the same style in mem freq init as in fsb freq init, returning
the value instead of assigning in multiple places.
Reviewed-by: Matt Roper <[email protected]>
Reviewed-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/f098ccdbb0c42016d5dad81e0b089bb4babe29f0.1718356614.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <[email protected]>
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| a8c026d0 | 30-Apr-2024 |
Matt Roper <[email protected]> |
drm/i915/bmg: BMG should re-use MTL's south display logic
Battlemage's south display is the same as Meteor Lake's, including the
need to invert the HPD pins, which Lunar Lake does not need.
Signed-
drm/i915/bmg: BMG should re-use MTL's south display logic
Battlemage's south display is the same as Meteor Lake's, including the
need to invert the HPD pins, which Lunar Lake does not need.
Signed-off-by: Matt Roper <[email protected]>
Signed-off-by: Balasubramani Vivekanandan <[email protected]>
Reviewed-by: Dnyaneshwar Bhadane <[email protected]>
Signed-off-by: Radhakrishna Sripada <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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| 65578d0d | 19-Sep-2023 |
Gustavo Sousa <[email protected]> |
drm/i915/xe2lpd: Add fake PCH
Xe2_LPD doesn't have south display engine on a PCH, it's actually
on the SoC die (while north display engine is on compute die). As
such it makes no sense to go through
drm/i915/xe2lpd: Add fake PCH
Xe2_LPD doesn't have south display engine on a PCH, it's actually
on the SoC die (while north display engine is on compute die). As
such it makes no sense to go through the PCI devices looking for
an ISA bridge. The approach used by BXT/GLK can't be used here since
leaving it with PCH_NONE would mean taking the wrong code paths.
For the places we currently use a PCH check, it's enough for now to just
check the north display version. Use that to define a fake PCH to be
used across the driver. Eventually these PCH checks may need to be
re-designed as this is already the third platform using/needing a
fake PCH.
v2: Match on display IP version rather than on platform (Matt Roper)
v3: Extend and clarify commit message (Matt Roper / Ville)
Signed-off-by: Gustavo Sousa <[email protected]>
Signed-off-by: Lucas De Marchi <[email protected]>
Reviewed-by: Matt Roper <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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