drm/amd/display: Allow reuse of of DCN4x codeRemove the static qualifier to make it available for code sharingwith other components.Reviewed-by: Charlene Liu <[email protected]>Signed-off-by
drm/amd/display: Allow reuse of of DCN4x codeRemove the static qualifier to make it available for code sharingwith other components.Reviewed-by: Charlene Liu <[email protected]>Signed-off-by: Dmytro <[email protected]>Signed-off-by: Charlene Liu <[email protected]>Signed-off-by: Alex Hung <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
show more ...
drm/amd/display: log destination of vertical interrupt[Why]Knowing the destination of OTG's vertical interrupt 2 is useful fordebugging, but it is not currently included in the OTG state readback
drm/amd/display: log destination of vertical interrupt[Why]Knowing the destination of OTG's vertical interrupt 2 is useful fordebugging, but it is not currently included in the OTG state readbacklogic[How]Read the OTG interrupt destination register to get the vertical interrupt2 destination on ASICs that have this register when reading back the OTGstate from hardwareReviewed-by: Sung Lee <[email protected]>Reviewed-by: Aric Cyr <[email protected]>Signed-off-by: Josip Pavic <[email protected]>Signed-off-by: Wayne Lin <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Add support for FAMS2+ interface versionsCurrent driver interface does not allow for flexibility in coexistenceof multiple interface versions, so add support for checking minorin
drm/amd/display: Add support for FAMS2+ interface versionsCurrent driver interface does not allow for flexibility in coexistenceof multiple interface versions, so add support for checking minorinterface revisions and providing appropriate programming.Tested-by: Daniel Wheeler <[email protected]>Reviewed-by: Alvin Lee <[email protected]>Signed-off-by: Dillon Varone <[email protected]>Signed-off-by: Rodrigo Siqueira <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Add 3DLUT FL HW bug workaround[Why]There is a known HW bug that causes the internal 3DLUT fetch signal tobe lost at VREADY, regardless of whether the OTG lock is being held orno
drm/amd/display: Add 3DLUT FL HW bug workaround[Why]There is a known HW bug that causes the internal 3DLUT fetch signal tobe lost at VREADY, regardless of whether the OTG lock is being held ornot. A workaround is necessary to make sure that this internal signalstays up after OTG unlock.[How]Set the 3DLUT_ENABLE bit immediately before and after the unlock. Alsouse VUPDATE_KEEPOUT to prevent lock transition in the region betweenVSTARTUP and VREADY, which could cause issues with this WA sequence.Also including misc. 3DLUT DMA-related sequence fixes to address a fewregressions causing corruption.Reviewed-by: Dillon Varone <[email protected]>Signed-off-by: Ilya Bakoulin <[email protected]>Signed-off-by: Roman Li <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Wait for all pending cleared before full update[Description]Before every full update we must wait for all pending updates to becleared - this is particularly important for minima
drm/amd/display: Wait for all pending cleared before full update[Description]Before every full update we must wait for all pending updates to becleared - this is particularly important for minimal transitionsbecause if we don't wait for pending cleared, it will be as ifthere was no minimal transition at all. In OTG we must read 3 differentstatus registers for pending cleared, one specifically for OTG updates,one specifically for OPTC updates, and the last for surface relatedupdates.Reviewed-by: Dillon Varone <[email protected]>Signed-off-by: Alvin Lee <[email protected]>Signed-off-by: Aurabindo Pillai <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Add P-State Keepout to dcn401 Global Sync[WHY&HOW]OTG has new functionality to allow P-State relative to VStartup. Keepout regionfor this should be configured based on DML output
drm/amd/display: Add P-State Keepout to dcn401 Global Sync[WHY&HOW]OTG has new functionality to allow P-State relative to VStartup. Keepout regionfor this should be configured based on DML outputs same as other global syncparams.Reviewed-by: Alvin Lee <[email protected]>Signed-off-by: Jerry Zuo <[email protected]>Signed-off-by: Dillon Varone <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Wait for double buffer update on ODM changes[WHAT & HOW]We must wait for ODM double buffer updates to completebefore exiting the pipe update sequence or we may reduceDISPCLK and
drm/amd/display: Wait for double buffer update on ODM changes[WHAT & HOW]We must wait for ODM double buffer updates to completebefore exiting the pipe update sequence or we may reduceDISPCLK and hit some transient underflow (pixel rate isreduced before the pipes have ODM enabled).Reviewed-by: Samson Tam <[email protected]>Cc: Mario Limonciello <[email protected]>Cc: Alex Deucher <[email protected]>Cc: [email protected]Signed-off-by: Alex Hung <[email protected]>Signed-off-by: Alvin Lee <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Updated optc401_set_drr to use dcn401 functionswhy:optc_401_set_drr was using an old optc3 function to update vtotal min and max,causing crashes when disabling FAMS2how:Update
drm/amd/display: Updated optc401_set_drr to use dcn401 functionswhy:optc_401_set_drr was using an old optc3 function to update vtotal min and max,causing crashes when disabling FAMS2how:Updated dcn401 to point to opt401 function for vtotal updates. This version ofthe function has FAMS2 logic that allows for FAMS2 to be disabled.Reviewed-by: Dillon Varone <[email protected]>Acked-by: Zaeem Mohamed <[email protected]>Signed-off-by: Relja Vojvodic <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split[WHY]Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODMpipesplit is used, pixels on the left edge of ODM s
drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split[WHY]Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODMpipesplit is used, pixels on the left edge of ODM slices need one extrapixel from the right edge of the previous slice to calculate the correctchroma value.Without this change, the chroma value is slightly different thanexpected. This is usually imperceptible visually, but it impacts testpattern CRCs for compliance test automation.[HOW]Update logic to use the register for adding extra left edge pixel forYCbCr422/420 ODM cases.Reviewed-by: George Shen <[email protected]>Acked-by: Alex Hung <[email protected]>Signed-off-by: Wenjing Liu <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: reset DSC clock in post unlock update[why]Switching between DSC clock or disable DSC block are not double buffered update.Corruption is observed if these updates happen before DS
drm/amd/display: reset DSC clock in post unlock update[why]Switching between DSC clock or disable DSC block are not double buffered update.Corruption is observed if these updates happen before DSC double buffereddisconnection.[how]Move DSC disable and refclk reset to post unlock update. Wait for DSC double buffereddisconnection and all mpccs are disconnected before reset DSC clock.Reviewed-by: Samson Tam <[email protected]>Acked-by: Tom Chung <[email protected]>Signed-off-by: Wenjing Liu <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: use even ODM slice width for two pixels per container[why]When optc uses two pixel per container, each ODM slice width must be aneven number.[how]If ODM slice width is odd num
drm/amd/display: use even ODM slice width for two pixels per container[why]When optc uses two pixel per container, each ODM slice width must be aneven number.[how]If ODM slice width is odd number increase it by 1.Reviewed-by: Dillon Varone <[email protected]>Acked-by: Wayne Lin <[email protected]>Signed-off-by: Wenjing Liu <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Address kdoc for 'Enable CRTC' in optc401_enable_crtcThis commit fixes the kdoc for 'Enable CRTC' in `optc401_enable_crtc`function.Fixes the below with gcc W=1:drivers/gpu/drm/
drm/amd/display: Address kdoc for 'Enable CRTC' in optc401_enable_crtcThis commit fixes the kdoc for 'Enable CRTC' in `optc401_enable_crtc`function.Fixes the below with gcc W=1:drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn401/dcn401_optc.c:177: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Enable CRTCFixes: 70839da63605 ("drm/amd/display: Add new DCN401 sources")Cc: Rodrigo Siqueira <[email protected]>Cc: Roman Li <[email protected]>Cc: Qingqing Zhuo <[email protected]>Cc: Aurabindo Pillai <[email protected]>Cc: Tom Chung <[email protected]>Signed-off-by: Srinivasan Shanmugam <[email protected]>Reviewed-by: Tom Chung <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Add new DCN401 sourcesAdd initial support for DCN 4.0.1.Signed-off-by: Aurabindo Pillai <[email protected]>Acked-by: Rodrigo Siqueira <[email protected]>Signed-of
drm/amd/display: Add new DCN401 sourcesAdd initial support for DCN 4.0.1.Signed-off-by: Aurabindo Pillai <[email protected]>Acked-by: Rodrigo Siqueira <[email protected]>Signed-off-by: Alex Deucher <[email protected]>