drm/amd/display: log destination of vertical interrupt[Why]Knowing the destination of OTG's vertical interrupt 2 is useful fordebugging, but it is not currently included in the OTG state readback
drm/amd/display: log destination of vertical interrupt[Why]Knowing the destination of OTG's vertical interrupt 2 is useful fordebugging, but it is not currently included in the OTG state readbacklogic[How]Read the OTG interrupt destination register to get the vertical interrupt2 destination on ASICs that have this register when reading back the OTGstate from hardwareReviewed-by: Sung Lee <[email protected]>Reviewed-by: Aric Cyr <[email protected]>Signed-off-by: Josip Pavic <[email protected]>Signed-off-by: Wayne Lin <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
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drm/amd/display: Add support to configure CRC window on specific CRC instance[Why]Have the need to specify the CRC window on specific CRC engine.dc_stream_configure_crc() today calculates CRC on
drm/amd/display: Add support to configure CRC window on specific CRC instance[Why]Have the need to specify the CRC window on specific CRC engine.dc_stream_configure_crc() today calculates CRC on crc engine 0 only and alwaysresets CRC engine at first.[How]Add index parameter to dc_stream_configure_crc() for selecting the desired crcengine. Additionally, add another parameter to specify whether to skip thedefault reset of crc engine.Reviewed-by: HaoPing Liu <[email protected]>Signed-off-by: Wayne Lin <[email protected]>Signed-off-by: Tom Chung <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Wait for all pending cleared before full update[Description]Before every full update we must wait for all pending updates to becleared - this is particularly important for minima
drm/amd/display: Wait for all pending cleared before full update[Description]Before every full update we must wait for all pending updates to becleared - this is particularly important for minimal transitionsbecause if we don't wait for pending cleared, it will be as ifthere was no minimal transition at all. In OTG we must read 3 differentstatus registers for pending cleared, one specifically for OTG updates,one specifically for OPTC updates, and the last for surface relatedupdates.Reviewed-by: Dillon Varone <[email protected]>Signed-off-by: Alvin Lee <[email protected]>Signed-off-by: Aurabindo Pillai <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amdgpu/display: Update kdoc for 'optc35_set_odm_combine'The parameters segment_width and last_segment_width are used to controlthe configuration of the Output Plane Processor (OPP), specifical
drm/amdgpu/display: Update kdoc for 'optc35_set_odm_combine'The parameters segment_width and last_segment_width are used to controlthe configuration of the Output Plane Processor (OPP), specifically thewidth of each segment that the display is divided into and the width ofthe last segmentFixes the below with gcc W=1:drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn35/dcn35_optc.c:59: warning: Function parameter or struct member 'segment_width' not described in 'optc35_set_odm_combine'drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn35/dcn35_optc.c:59: warning: Function parameter or struct member 'last_segment_width' not described in 'optc35_set_odm_combine'drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn35/dcn35_optc.c:59: warning: Excess function parameter 'timing' description in 'optc35_set_odm_combine'Cc: Tom Chung <[email protected]>Cc: Rodrigo Siqueira <[email protected]>Cc: Roman Li <[email protected]>Cc: Aurabindo Pillai <[email protected]>Signed-off-by: Srinivasan Shanmugam <[email protected]>Reviewed-by: Tom Chung <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split[WHY]Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODMpipesplit is used, pixels on the left edge of ODM s
drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split[WHY]Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODMpipesplit is used, pixels on the left edge of ODM slices need one extrapixel from the right edge of the previous slice to calculate the correctchroma value.Without this change, the chroma value is slightly different thanexpected. This is usually imperceptible visually, but it impacts testpattern CRCs for compliance test automation.[HOW]Update logic to use the register for adding extra left edge pixel forYCbCr422/420 ODM cases.Reviewed-by: George Shen <[email protected]>Acked-by: Alex Hung <[email protected]>Signed-off-by: Wenjing Liu <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: use even ODM slice width for two pixels per container[why]When optc uses two pixel per container, each ODM slice width must be aneven number.[how]If ODM slice width is odd num
drm/amd/display: use even ODM slice width for two pixels per container[why]When optc uses two pixel per container, each ODM slice width must be aneven number.[how]If ODM slice width is odd number increase it by 1.Reviewed-by: Dillon Varone <[email protected]>Acked-by: Wayne Lin <[email protected]>Signed-off-by: Wenjing Liu <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Support long vblank feature[WHY]We want to support low hz case, but the originalvtotal/vtotal_min/vtotal_max can't support morethan 0x7FFF.[HOW]We use the 2 HW reg to contorl
drm/amd/display: Support long vblank feature[WHY]We want to support low hz case, but the originalvtotal/vtotal_min/vtotal_max can't support morethan 0x7FFF.[HOW]We use the 2 HW reg to contorl long vblank case.1. OTG_V_COUNT_STOP_CONTROL -> vcount_stop2. OTG_V_COUNT_STOP_CONTROL2 -> vcount_stop_timervcount_stop define from which line we stop using vcountand start using vcount2.vcount_stop_timer define how long we use vcount2.Ex:Vtotal = 7OTG_V_COUNT_STOP_CONTROL = 4OTG_V_COUNT_STOP_CONTROL2 = 5time : 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11vcount : 0, 1, 2, 3, - - - - - 4, 5, 6vcount2 : 0, 1, 2, 3, 4,Reviewed-by: Jun Lei <[email protected]>Acked-by: Alex Hung <[email protected]>Signed-off-by: ChunTao Tso <[email protected]>Signed-off-by: Robin Chen<[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Clear OPTC mem select on disable[Why]Not clearing the memory select bits prior to OPTC disable can cause DSCcorruption issues when attempting to reuse a memory instance for anoth
drm/amd/display: Clear OPTC mem select on disable[Why]Not clearing the memory select bits prior to OPTC disable can cause DSCcorruption issues when attempting to reuse a memory instance for anotherOPTC that enables ODM.[How]Clear the memory select bits prior to disabling an OPTC.Cc: Mario Limonciello <[email protected]>Cc: Alex Deucher <[email protected]>Cc: [email protected]Reviewed-by: Charlene Liu <[email protected]>Acked-by: Alex Hung <[email protected]>Signed-off-by: Ilya Bakoulin <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Disconnect phantom pipe OPP from OPTC being disabled[Why]If an OPP is used for a different OPTC without first being disconnectedfrom the previous OPTC, unexpected behaviour can o
drm/amd/display: Disconnect phantom pipe OPP from OPTC being disabled[Why]If an OPP is used for a different OPTC without first being disconnectedfrom the previous OPTC, unexpected behaviour can occur. This alsoapplies to phantom pipes, which is what the current logic missed.[How]Disconnect OPPs from OPTC for phantom pipes before disabling OTG master.Also move the disconnection to before the OTG master disable, since theregister is double buffered.Reviewed-by: Dillon Varone <[email protected]>Acked-by: Rodrigo Siqueira <[email protected]>Signed-off-by: George Shen <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Fix hang/underflow when transitioning to ODM4:1[Why]Under some circumstances, disabling an OPTC and attempting to reclaimits OPP(s) for a different OPTC could cause a hang/underf
drm/amd/display: Fix hang/underflow when transitioning to ODM4:1[Why]Under some circumstances, disabling an OPTC and attempting to reclaimits OPP(s) for a different OPTC could cause a hang/underflow due to OPPsnot being properly disconnected from the disabled OPTC.[How]Ensure that all OPPs are unassigned from an OPTC when it gets disabled.Reviewed-by: Alvin Lee <[email protected]>Acked-by: Wayne Lin <[email protected]>Signed-off-by: Ilya Bakoulin <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Refactor OPTC into component folder[why]Move all optc files to uniquefolder optc.[how]creating optc repo in dc, and moved the dcnxx_optc.c and .h files intocorresponding new
drm/amd/display: Refactor OPTC into component folder[why]Move all optc files to uniquefolder optc.[how]creating optc repo in dc, and moved the dcnxx_optc.c and .h files intocorresponding new folders inside the optc and cleared the linkageerrors by adding relative paths in the Makefile.template.Reviewed-by: Martin Leung <[email protected]>Acked-by: Hamza Mahfooz <[email protected]>Signed-off-by: Parandhaman K <[email protected]>Signed-off-by: Alex Deucher <[email protected]>