drm/amd/display: Remove unused hubbub1_toggle_watermark_change_reqhubbub1_toggle_watermark_change_req() last use was removed in 2017 bycommit b8fce2c9d773 ("drm/amd/display: Optimize programming f
drm/amd/display: Remove unused hubbub1_toggle_watermark_change_reqhubbub1_toggle_watermark_change_req() last use was removed in 2017 bycommit b8fce2c9d773 ("drm/amd/display: Optimize programming front end")Remove it.Signed-off-by: Dr. David Alan Gilbert <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
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drm/amd/display: Allow reuse of of DCN4x codeRemove the static qualifier to make it available for code sharingwith other components.Reviewed-by: Charlene Liu <[email protected]>Signed-off-by
drm/amd/display: Allow reuse of of DCN4x codeRemove the static qualifier to make it available for code sharingwith other components.Reviewed-by: Charlene Liu <[email protected]>Signed-off-by: Dmytro <[email protected]>Signed-off-by: Charlene Liu <[email protected]>Signed-off-by: Alex Hung <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Fix seamless boot sequence[WHY]When the system powers up eDP with external monitors in seamless bootsequence, stutter get enabled before TTU and HUBP registers beingprogrammed,
drm/amd/display: Fix seamless boot sequence[WHY]When the system powers up eDP with external monitors in seamless bootsequence, stutter get enabled before TTU and HUBP registers beingprogrammed, which resulting in underflow.[HOW]Enable TTU in hubp_init.Change the sequence that do not perpare_bandwidth and optimize_bandwidthwhile having seamless boot streams.Cc: Mario Limonciello <[email protected]>Cc: Alex Deucher <[email protected]>Cc: [email protected]Reviewed-by: Nicholas Kazlauskas <[email protected]>Signed-off-by: Lo-an Chen <[email protected]>Signed-off-by: Paul Hsieh <[email protected]>Signed-off-by: Alex Hung <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Enable Request rate limiter during C-State on dcn401[WHY]When C-State entry is requested, the rate limiter will be disabledwhich can result in high contention in the DCHUB return
drm/amd/display: Enable Request rate limiter during C-State on dcn401[WHY]When C-State entry is requested, the rate limiter will be disabledwhich can result in high contention in the DCHUB return path.[HOW]Enable the rate limiter during C-state requests to prevent contention.Cc: [email protected] # 6.11+Reviewed-by: Alvin Lee <[email protected]>Signed-off-by: Dillon Varone <[email protected]>Signed-off-by: Hamza Mahfooz <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Add P-State Stall Timeout Recovery Support for dcn401[WHY&HOW]Adds support for P-State stall timeout detection in DCHUBBUB.Reviewed-by: Alvin Lee <[email protected]>Signed-off
drm/amd/display: Add P-State Stall Timeout Recovery Support for dcn401[WHY&HOW]Adds support for P-State stall timeout detection in DCHUBBUB.Reviewed-by: Alvin Lee <[email protected]>Signed-off-by: Dillon Varone <[email protected]>Signed-off-by: Tom Chung <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Clear cached watermark after resume[WHY]Driver could skip program watermarks when resume from S0i3/S4.[HOW]Clear the cached one first to make sure new value gets applied.Revi
drm/amd/display: Clear cached watermark after resume[WHY]Driver could skip program watermarks when resume from S0i3/S4.[HOW]Clear the cached one first to make sure new value gets applied.Reviewed-by: Alvin Lee <[email protected]>Reviewed-by: Roman Li <[email protected]>Signed-off-by: Charlene Liu <[email protected]>Signed-off-by: Alex Hung <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Unlock Pipes Based On DET Allocation[Why]DML21 does not allocate DET evenly between pipes.May result in underflow when unlocking the pipes as DET couldbe overallocated.[How]1
drm/amd/display: Unlock Pipes Based On DET Allocation[Why]DML21 does not allocate DET evenly between pipes.May result in underflow when unlocking the pipes as DET couldbe overallocated.[How]1. Unlock pipes that have a decreased amount of DET allocation2. Wait for the double buffer to be updated.3. Unlock the remaining pipes.Reviewed-by: Alvin Lee <[email protected]>Signed-off-by: Austin Zheng <[email protected]>Signed-off-by: Tom Chung <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: rename dcn3/dcn4 to more sound termsUse more accurate names to refer to the asic architecture.dcn3 in DML actually refers to DCN32 and DCN321, so rename it to dcn32xdcn4 refers t
drm/amd/display: rename dcn3/dcn4 to more sound termsUse more accurate names to refer to the asic architecture.dcn3 in DML actually refers to DCN32 and DCN321, so rename it to dcn32xdcn4 refers to any DCN4x soc., and hence rename dcn4 to dcn4xReviewed-by: Rodrigo Siqueira <[email protected]>Signed-off-by: Aurabindo Pillai <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Add ASIC cap to limit DCC surface width[Why]Certain configurations of DCN401 require ODM4:1 to support DCC for 10Ksurfaces. DCC should be conservatively disabled in those cases.
drm/amd/display: Add ASIC cap to limit DCC surface width[Why]Certain configurations of DCN401 require ODM4:1 to support DCC for 10Ksurfaces. DCC should be conservatively disabled in those cases.The issue is that current logic limits 10K surface DCC for allconfigurations of DCN401.[How]Add DC ASIC cap to indicate max surface width that can support DCC.Disable DCC if this ASIC cap is non-zero and surface width exceeds it.Reviewed-by: Jun Lei <[email protected]>Signed-off-by: Jerry Zuo <[email protected]>Signed-off-by: George Shen <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Enable DCC on DCN401[WHAT]Add registers and entry points to enable DCC on DCN4xReviewed-by: Rodrigo Siqueira <[email protected]>Signed-off-by: Alex Hung <[email protected]
drm/amd/display: Enable DCC on DCN401[WHAT]Add registers and entry points to enable DCC on DCN4xReviewed-by: Rodrigo Siqueira <[email protected]>Signed-off-by: Alex Hung <[email protected]>Signed-off-by: Aurabindo Pillai <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Validate function returns[WHAT & HOW]Function return values must be checked before data can be usedin subsequent functions.This fixes 4 CHECKED_RETURN issues reported by Coveri
drm/amd/display: Validate function returns[WHAT & HOW]Function return values must be checked before data can be usedin subsequent functions.This fixes 4 CHECKED_RETURN issues reported by Coverity.Reviewed-by: Harry Wentland <[email protected]>Signed-off-by: Alex Hung <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Support new VA page table block size[Why]Page table definition increased up to 2MB.[How]Define new use case of page table for VA.Reviewed-by: Alvin Lee <[email protected]>A
drm/amd/display: Support new VA page table block size[Why]Page table definition increased up to 2MB.[How]Define new use case of page table for VA.Reviewed-by: Alvin Lee <[email protected]>Acked-by: Zaeem Mohamed <[email protected]>Signed-off-by: Chris Park <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Remove unused codeThis commit removes some unused code with the required adjustments.Signed-off-by: Rodrigo Siqueira <[email protected]>Acked-by: Harry Wentland <harry.we
drm/amd/display: Remove unused codeThis commit removes some unused code with the required adjustments.Signed-off-by: Rodrigo Siqueira <[email protected]>Acked-by: Harry Wentland <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Refactor HUBBUB into component folder for DCN401[why]Cleaning up the code refactor requires hubbub to be in its owncomponent.[how]Move all DCN401 files under newly created hub
drm/amd/display: Refactor HUBBUB into component folder for DCN401[why]Cleaning up the code refactor requires hubbub to be in its owncomponent.[how]Move all DCN401 files under newly created hubbub folder and fixing themakefiles.Reviewed-by: Rodrigo Siqueira <[email protected]>Signed-off-by: Harikrishna Revalla <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Refactor HUBBUB into component folder[why]cleaning up the code refactor requires hubbub to be in its own component.[how]Move all files under newly created hubbub folder and fix
drm/amd/display: Refactor HUBBUB into component folder[why]cleaning up the code refactor requires hubbub to be in its own component.[how]Move all files under newly created hubbub folder and fix the makefiles.Reviewed-by: Martin Leung <[email protected]>Acked-by: Wayne Lin <[email protected]>Signed-off-by: Revalla Hari Krishna <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>