drm/amd/display: update dcn351 used clock offset

[why]
hw register offset delta

Reviewed-by: Martin Leung <[email protected]>
Signed-off-by: Charlene Liu <[email protected]>
Signed-off-by: Au

drm/amd/display: update dcn351 used clock offset

[why]
hw register offset delta

Reviewed-by: Martin Leung <[email protected]>
Signed-off-by: Charlene Liu <[email protected]>
Signed-off-by: Aurabindo Pillai <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Adjust incorrect indentations and spaces

This fixes indentations and adjust spaces for better readability and
code styles.

Reviewed-by: Rodrigo Siqueira <[email protected]>

drm/amd/display: Adjust incorrect indentations and spaces

This fixes indentations and adjust spaces for better readability and
code styles.

Reviewed-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Hung <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Add misc DC changes for DCN401

Add miscellaneous changes to enable DCN401 init

Signed-off-by: Aurabindo Pillai <[email protected]>
Acked-by: Rodrigo Siqueira <rodrigo.siquei

drm/amd/display: Add misc DC changes for DCN401

Add miscellaneous changes to enable DCN401 init

Signed-off-by: Aurabindo Pillai <[email protected]>
Acked-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Add DCN35 CLK_MGR

[Why & How]
Add CLK_MGR handling for DCN35.

v2: Drop stale SMU interfaces (Alex)

Signed-off-by: Qingqing Zhuo <[email protected]>
Acked-by: Harry Wentland <H

drm/amd/display: Add DCN35 CLK_MGR

[Why & How]
Add CLK_MGR handling for DCN35.

v2: Drop stale SMU interfaces (Alex)

Signed-off-by: Qingqing Zhuo <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Rename DCN config to FP

[Why & How]
The only reason we have the DCN config is for
floating point support. Rename it to make that
clear and (hopefully) avoid misuse of the config
in

drm/amd/display: Rename DCN config to FP

[Why & How]
The only reason we have the DCN config is for
floating point support. Rename it to make that
clear and (hopefully) avoid misuse of the config
in the future.

Reviewed-by: Rodrigo Siqueira <[email protected]>
Acked-by: Qingqing Zhuo <[email protected]>
Signed-off-by: Harry Wentland <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: move FPU code from dcn301 clk mgr to DML folder

The -mno-gnu-attribute option in dcn301 clk mgr makefile hides a soft vs
hard fp error for powerpc. After removing this flag, we can

drm/amd/display: move FPU code from dcn301 clk mgr to DML folder

The -mno-gnu-attribute option in dcn301 clk mgr makefile hides a soft vs
hard fp error for powerpc. After removing this flag, we can see some FPU
code remains there:

gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses
hard float,
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.o
uses soft float

Therefore, remove the -mno-gnu-attribute flag for dcn301/powerpc and
move FPU-associated code to DML folder.

Signed-off-by: Melissa Wen <[email protected]>
Reviewed-by: Maíra Canal <[email protected]>
Reviewed-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: move FPU code from dcn30 clk mgr to DML folder

The -mno-gnu-attribute option in clk mgr makefile for dcn30 hides a soft
vs hard fp error for powerpc. After removing this flag, we ca

drm/amd/display: move FPU code from dcn30 clk mgr to DML folder

The -mno-gnu-attribute option in clk mgr makefile for dcn30 hides a soft
vs hard fp error for powerpc. After removing this flag, we can see some
FPU code remains there:

gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses
hard float,
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.o
uses soft float

Therefore, remove the -mno-gnu-attribute flag for dcn30/powerpc and move
FPU-associated code to DML folder.

Signed-off-by: Melissa Wen <[email protected]>
Reviewed-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: move FPU code on dcn21 clk_mgr

The -mno-gnu-attribute option in dcn21 clk mgr makefile hides a soft vs
hard fp error for powerpc. After removing this flag, we can see some FPU
code

drm/amd/display: move FPU code on dcn21 clk_mgr

The -mno-gnu-attribute option in dcn21 clk mgr makefile hides a soft vs
hard fp error for powerpc. After removing this flag, we can see some FPU
code remains there:

/gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses
hard float,
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.o uses
soft float

Therefore, remove the -mno-gnu-attribute flag for dcn21/powerpc and move
FPU-associated code to DML folder.

Signed-off-by: Melissa Wen <[email protected]>
Reviewed-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Drop FPU flags from dcn32_clk_mgr

We are working to isolate FPU operations inside the DML folder, and the
file dcn32_clk_mgr has some of these operations. This commit moves the
FPU

drm/amd/display: Drop FPU flags from dcn32_clk_mgr

We are working to isolate FPU operations inside the DML folder, and the
file dcn32_clk_mgr has some of these operations. This commit moves the
FPU operations inside the clock manager and creates the dcn32_fpu file
to aggregate those operations. Note that there is no functional change
ere, just moving code from one part to another.

Tested-by: Daniel Wheeler <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Enable DCN314 in DC

Add support for DCN 3.1.4 in Display Core

Signed-off-by: Roman Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/display: make FP handling in Makefiles consistent

Use the same pattern as the DML Makefile and while we are here
add a missing x86 guard around the msse flags for DCN3.2.x.

Reviewed-by:

drm/amdgpu/display: make FP handling in Makefiles consistent

Use the same pattern as the DML Makefile and while we are here
add a missing x86 guard around the msse flags for DCN3.2.x.

Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: add CLKMGR changes for DCN32/321

Add support for managing DCN3.2.x clocks.

v2: squash in smu interface updates (Alex)
v3: Drop unused SMU header (Alex)

Signed-off-by: Aurabindo Pi

drm/amd/display: add CLKMGR changes for DCN32/321

Add support for managing DCN3.2.x clocks.

v2: squash in smu interface updates (Alex)
v3: Drop unused SMU header (Alex)

Signed-off-by: Aurabindo Pillai <[email protected]>
Acked-by: Jerry Zuo <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Add DCN315 CLK_MGR

Clk and SMU interfaces for DCN 3.1.5.

Signed-off-by: Qingqing Zhuo <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex

drm/amd/display: Add DCN315 CLK_MGR

Clk and SMU interfaces for DCN 3.1.5.

Signed-off-by: Qingqing Zhuo <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Add DCN316 resource and SMU clock manager

Add core DC implementation for DCN316.

Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Prike Liang <[email protected]>
Review

drm/amd/display: Add DCN316 resource and SMU clock manager

Add core DC implementation for DCN316.

Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Prike Liang <[email protected]>
Reviewed-by: Leo Li <[email protected]>
Signed-off-by: Hansen Dsouza <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu/display: fold DRM_AMD_DC_DCN201 into DRM_AMD_DC_DCN

No need for a separate kconfig option at this point.

Reviewed-by: Zhan Liu <[email protected]>
Signed-off-by: Alex Deucher <alexander.d

drm/amdgpu/display: fold DRM_AMD_DC_DCN201 into DRM_AMD_DC_DCN

No need for a separate kconfig option at this point.

Reviewed-by: Zhan Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: add cyan_skillfish display support

[Why]
add display related cyan_skillfish files in.

makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag.

v2: squash in clang fixes from Harry, N

drm/amd/display: add cyan_skillfish display support

[Why]
add display related cyan_skillfish files in.

makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag.

v2: squash in clang fixes from Harry, Nathan
v3: squash in missing CONFIG_DRM_AMD_DC check (Alex)

Signed-off-by: Charlene Liu <[email protected]>
Signed-off-by: Zhan Liu <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Jun Lei <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN

No need for a separate flag now that DCN3.1 is not in bring up.
Fold into DRM_AMD_DC_DCN like previous DCN IPs.

Reviewed-by: Nicholas

drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN

No need for a separate flag now that DCN3.1 is not in bring up.
Fold into DRM_AMD_DC_DCN like previous DCN IPs.

Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Add DCN3.1 clock manager support

Adds support for clock requests for the various parts of the DCN3.1 IP
and the interfaces and definitions for sending messages to SMU/PMFW.

Include

drm/amd/display: Add DCN3.1 clock manager support

Adds support for clock requests for the various parts of the DCN3.1 IP
and the interfaces and definitions for sending messages to SMU/PMFW.

Includes new support for z9/10, detecting SMU timeout and p-state
support enablement.

Acked-by: Huang Rui <[email protected]>
Signed-off-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu/display: drop DCN support for aarch64

From Ard:

"Simply disabling -mgeneral-regs-only left and right is risky, given that
the standard AArch64 ABI permits the use of FP/SIMD registers an

drm/amdgpu/display: drop DCN support for aarch64

From Ard:

"Simply disabling -mgeneral-regs-only left and right is risky, given that
the standard AArch64 ABI permits the use of FP/SIMD registers anywhere,
and GCC is known to use SIMD registers for spilling, and may invent
other uses of the FP/SIMD register file that have nothing to do with the
floating point code in question. Note that putting kernel_neon_begin()
and kernel_neon_end() around the code that does use FP is not sufficient
here, the problem is in all the other code that may be emitted with
references to SIMD registers in it.

So the only way to do this properly is to put all floating point code in
a separate compilation unit, and only compile that unit with
-mgeneral-regs-only."

Disable support until the code can be properly refactored to support this
properly on aarch64.

Acked-by: Will Deacon <[email protected]>
Reported-by: Ard Biesheuvel <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu/display: drop DCN support for aarch64

From Ard:

"Simply disabling -mgeneral-regs-only left and right is risky, given that
the standard AArch64 ABI permits the use of FP/SIMD registers an

drm/amdgpu/display: drop DCN support for aarch64

From Ard:

"Simply disabling -mgeneral-regs-only left and right is risky, given that
the standard AArch64 ABI permits the use of FP/SIMD registers anywhere,
and GCC is known to use SIMD registers for spilling, and may invent
other uses of the FP/SIMD register file that have nothing to do with the
floating point code in question. Note that putting kernel_neon_begin()
and kernel_neon_end() around the code that does use FP is not sufficient
here, the problem is in all the other code that may be emitted with
references to SIMD registers in it.

So the only way to do this properly is to put all floating point code in
a separate compilation unit, and only compile that unit with
-mgeneral-regs-only."

Disable support until the code can be properly refactored to support this
properly on aarch64.

Acked-by: Will Deacon <[email protected]>
Reported-by: Ard Biesheuvel <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu/display: FP fixes for DCN3.x (v4)

Add proper FP_START/END handling and adjust Makefiles per
previous asics.

v2: fix up harder.
v3: fix clkmgr Makefile for dcn30
v4: fix old gcc handling

drm/amdgpu/display: FP fixes for DCN3.x (v4)

Add proper FP_START/END handling and adjust Makefiles per
previous asics.

v2: fix up harder.
v3: fix clkmgr Makefile for dcn30
v4: fix old gcc handling is only required for x86

Build-tested-by: Nathan Chancellor <[email protected]>
Reviewed-by: Harry Wentland <[email protected]> (v1)
Reviewed-by: Nicholas Kazlauskas <[email protected]> (v1)
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)

Avoids confusion in configurations.

v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled
v3: rebase on latest code

Reviewed

drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)

Avoids confusion in configurations.

v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled
v3: rebase on latest code

Reviewed-by: Luben Tuikov <[email protected]> (v1)
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Add dcn3.01 support to DC (v2)

Update dc for vangogh support.

v2: fix compilation without DCN 301 set.

Signed-off-by: Roman Li <[email protected]>
Signed-off-by: Alex Deucher <alex

drm/amd/display: Add dcn3.01 support to DC (v2)

Update dc for vangogh support.

v2: fix compilation without DCN 301 set.

Signed-off-by: Roman Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: add DCN support for aarch64

This adds ARM64 support into the DCN. This mainly enables support
for Navi graphics cards. The dcn10 changes haven't been tested,
since I don't have the

drm/amd/display: add DCN support for aarch64

This adds ARM64 support into the DCN. This mainly enables support
for Navi graphics cards. The dcn10 changes haven't been tested,
since I don't have the relevant hardware available, but there
is no way to conditionally disable them, so I've done them anyway.

Signed-off-by: Daniel Kolesa <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: dc/clk_mgr: add support for SI parts (v2)

(v1) Changelog

[Why]
After commit c69dd2d "drm/amd/display: Refactor clk_mgr functions"
dc/clk_mgr requires these changes to add SI parts

drm/amd/display: dc/clk_mgr: add support for SI parts (v2)

(v1) Changelog

[Why]
After commit c69dd2d "drm/amd/display: Refactor clk_mgr functions"
dc/clk_mgr requires these changes to add SI parts support
Necessary to avoid hitting default: ASSERT(0); /* Unknown Asic */
that would cause kernel freeze

[How]
Add case statement for FAMILY_SI chipsets

(v2) Changelog

[Why]
DCE6 has no DPREFCLK_CNTL register

[How]
Add DCE6 specific macros definitions for CLK registers and masks
Add DCE6 specific dce60/dce60_clk_mgr.c for DCE6 customization
Code style: reuse all the public functions in dce100/dce_clk_mgr.h header
Code style: use dce60_* static functions as per other DCE implementations
Add dce60_get_dp_ref_freq_khz() w/o using DPREFCLK_CNTL register
Use dce60_get_dp_ref_freq_khz() function in dce60_funcs
Add DCE6 specific dce60_clk_mgr_construct
dc/clk_mgr/dce_clk_mgr.c: use dce60_clk_mgr_construct for FAMILY_SI chipsets
Add Makefile rules for dce60_clk_mgr.o target conditional to CONFIG_DRM_AMD_DC_SI

Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Mauro Rossi <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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