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Revision tags: v6.15, v6.15-rc7, v6.15-rc6, v6.15-rc5, v6.15-rc4, v6.15-rc3, v6.15-rc2, v6.15-rc1, v6.14, v6.14-rc7, v6.14-rc6, v6.14-rc5, v6.14-rc4, v6.14-rc3, v6.14-rc2, v6.14-rc1, v6.13, v6.13-rc7, v6.13-rc6, v6.13-rc5, v6.13-rc4, v6.13-rc3, v6.13-rc2, v6.13-rc1, v6.12, v6.12-rc7, v6.12-rc6, v6.12-rc5, v6.12-rc4, v6.12-rc3, v6.12-rc2, v6.12-rc1 |
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| #
c29aeadf |
| 20-Sep-2024 |
Lijo Lazar <[email protected]> |
drm/amdgpu: Add NPS switch support for GC 9.4.3
Add dynamic NPS switch support for GC 9.4.3 variants. Only GC v9.4.3 and
GC v9.4.4 currently support this. NPS switch is only supported if an SOC
supp
drm/amdgpu: Add NPS switch support for GC 9.4.3
Add dynamic NPS switch support for GC 9.4.3 variants. Only GC v9.4.3 and
GC v9.4.4 currently support this. NPS switch is only supported if an SOC
supports multiple NPS modes.
Signed-off-by: Lijo Lazar <[email protected]>
Signed-off-by: Rajneesh Bhardwaj <[email protected]>
Reviewed-by: Feifei Xu <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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Revision tags: v6.11, v6.11-rc7, v6.11-rc6, v6.11-rc5, v6.11-rc4, v6.11-rc3, v6.11-rc2, v6.11-rc1, v6.10, v6.10-rc7, v6.10-rc6, v6.10-rc5, v6.10-rc4, v6.10-rc3, v6.10-rc2, v6.10-rc1, v6.9, v6.9-rc7, v6.9-rc6, v6.9-rc5, v6.9-rc4 |
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| #
0617cdde |
| 14-Apr-2024 |
Alex Deucher <[email protected]> |
drm/amdgpu: add nbio set_reg_remap helper
Will be used to consolidate reg remap settings and fix HDP
flushes on systems with non-4K pages.
Reviewed-by: Felix Kuehling <[email protected]>
Signe
drm/amdgpu: add nbio set_reg_remap helper
Will be used to consolidate reg remap settings and fix HDP
flushes on systems with non-4K pages.
Reviewed-by: Felix Kuehling <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Revision tags: v6.9-rc3, v6.9-rc2, v6.9-rc1, v6.8, v6.8-rc7, v6.8-rc6, v6.8-rc5 |
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| #
c607e76e |
| 16-Feb-2024 |
Asad Kamal <[email protected]> |
Revert "drm/amdgpu: Add pcie usage callback to nbio"
pcie usage is now handled by fw
This reverts commit 8d759dc6644df4141a151293cb0e77fd8ca379ed.
Signed-off-by: Asad Kamal <[email protected]>
Re
Revert "drm/amdgpu: Add pcie usage callback to nbio"
pcie usage is now handled by fw
This reverts commit 8d759dc6644df4141a151293cb0e77fd8ca379ed.
Signed-off-by: Asad Kamal <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Revision tags: v6.8-rc4, v6.8-rc3, v6.8-rc2, v6.8-rc1, v6.7, v6.7-rc8, v6.7-rc7, v6.7-rc6, v6.7-rc5, v6.7-rc4, v6.7-rc3, v6.7-rc2, v6.7-rc1, v6.6, v6.6-rc7, v6.6-rc6, v6.6-rc5, v6.6-rc4, v6.6-rc3, v6.6-rc2, v6.6-rc1, v6.5, v6.5-rc7, v6.5-rc6, v6.5-rc5, v6.5-rc4, v6.5-rc3 |
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| #
75fdd738 |
| 18-Jul-2023 |
Lang Yu <[email protected]> |
drm/amdgpu: add nbio callback for VPE
Add nbio callback to configure doorbell settings.
Signed-off-by: Lang Yu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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| #
8d759dc6 |
| 28-Jul-2023 |
Asad Kamal <[email protected]> |
drm/amdgpu: Add pcie usage callback to nbio
Add a callback in nbio to get pcie usage
Signed-off-by: Asad Kamal <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Reviewed-by: Shiwu Z
drm/amdgpu: Add pcie usage callback to nbio
Add a callback in nbio to get pcie usage
Signed-off-by: Asad Kamal <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Reviewed-by: Shiwu Zhang <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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| #
900af4e4 |
| 27-Jul-2023 |
Lijo Lazar <[email protected]> |
drm/amdgpu: Add pcie replay count callback to nbio
Add a callback in nbio to get pcie replay count.
Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
drm/amdgpu: Add pcie replay count callback to nbio
Add a callback in nbio to get pcie replay count.
Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Revision tags: v6.5-rc2, v6.5-rc1, v6.4, v6.4-rc7 |
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| #
0e41639d |
| 13-Jun-2023 |
Lijo Lazar <[email protected]> |
drm/amdgpu: Remove unused NBIO interface
Set compute partition mode interface in NBIO is no longer used. Remove
the only implementation from NBIO v7.9
Signed-off-by: Lijo Lazar <[email protected]>
drm/amdgpu: Remove unused NBIO interface
Set compute partition mode interface in NBIO is no longer used. Remove
the only implementation from NBIO v7.9
Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: Le Ma <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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Revision tags: v6.4-rc6, v6.4-rc5, v6.4-rc4, v6.4-rc3, v6.4-rc2, v6.4-rc1, v6.3, v6.3-rc7, v6.3-rc6, v6.3-rc5, v6.3-rc4, v6.3-rc3, v6.3-rc2, v6.3-rc1, v6.2 |
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| #
0f2e1d62 |
| 17-Feb-2023 |
Lijo Lazar <[email protected]> |
drm/amdgpu: Get supported memory partition modes
Expand the interface to get supported memory partition modes also along
with the current memory partition mode.
Signed-off-by: Lijo Lazar <lijo.laza
drm/amdgpu: Get supported memory partition modes
Expand the interface to get supported memory partition modes also along
with the current memory partition mode.
Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Le Ma <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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Revision tags: v6.2-rc8, v6.2-rc7, v6.2-rc6, v6.2-rc5, v6.2-rc4, v6.2-rc3, v6.2-rc2, v6.2-rc1, v6.1, v6.1-rc8, v6.1-rc7, v6.1-rc6, v6.1-rc5, v6.1-rc4, v6.1-rc3, v6.1-rc2, v6.1-rc1, v6.0, v6.0-rc7, v6.0-rc6 |
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| #
75d16923 |
| 16-Sep-2022 |
Lijo Lazar <[email protected]> |
drm/amdgpu: Add initial version of XCP routines
Within a device, an accelerator core partition can be constituted with
different IP instances. These partitions are spatial in nature. Number
of parti
drm/amdgpu: Add initial version of XCP routines
Within a device, an accelerator core partition can be constituted with
different IP instances. These partitions are spatial in nature. Number
of partitions which can exist at the same time depends on the 'partition
mode'. Add a manager entity which is responsible for switching between
different partition modes and maintaining partitions. It is also
responsible for suspend/resume of different partitions.
Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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Revision tags: v6.0-rc5, v6.0-rc4, v6.0-rc3, v6.0-rc2, v6.0-rc1, v5.19, v5.19-rc8, v5.19-rc7, v5.19-rc6, v5.19-rc5, v5.19-rc4, v5.19-rc3, v5.19-rc2, v5.19-rc1, v5.18, v5.18-rc7, v5.18-rc6, v5.18-rc5, v5.18-rc4, v5.18-rc3, v5.18-rc2 |
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| #
ea2d2f8e |
| 05-Apr-2022 |
Rajneesh Bhardwaj <[email protected]> |
drm/amdgpu: detect current GPU memory partition mode
- Add helpers to detect the current GPU memory partition.
- Add current memory partition mode sysfs node.
Tested-by: Ori Messinger <Ori.Messin
drm/amdgpu: detect current GPU memory partition mode
- Add helpers to detect the current GPU memory partition.
- Add current memory partition mode sysfs node.
Tested-by: Ori Messinger <[email protected]>
Reviewed-by: Felix Kuehling <[email protected]>
Signed-off-by: Rajneesh Bhardwaj <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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Revision tags: v5.18-rc1 |
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| #
0c552ed3 |
| 02-Apr-2022 |
Le Ma <[email protected]> |
drm/amdgpu: add indirect r/w interface for smn address greater than 32bits
On multiple AIDs platform, bit[34:32] in SMD address is leveraged to access
nonAID0 register smn address and new PCI_INDEX_
drm/amdgpu: add indirect r/w interface for smn address greater than 32bits
On multiple AIDs platform, bit[34:32] in SMD address is leveraged to access
nonAID0 register smn address and new PCI_INDEX_HI register is introduced
to access the higher bits.
v2: rebase on latest register accessors (Alex)
Signed-off-by: Le Ma <[email protected]>
Acked-by: Felix Kuehling <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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| #
98a54e88 |
| 17-May-2022 |
Le Ma <[email protected]> |
drm/amdgpu: add sysfs node for compute partition mode
Add current/available compute partitin mode sysfs node.
v2: make the sysfs node as IP independent one in amdgpu_gfx.c
Signed-off-by: Le Ma <le
drm/amdgpu: add sysfs node for compute partition mode
Add current/available compute partitin mode sysfs node.
v2: make the sysfs node as IP independent one in amdgpu_gfx.c
Signed-off-by: Le Ma <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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| #
fdc94d3a |
| 13-Mar-2023 |
Hawking Zhang <[email protected]> |
drm/amdgpu: Rework pcie_bif ras sw_init
pcie_bif ras blocks needs to be initialized as early
as possible to handle fatal error detected in hw_init
phase. also align the pcie_bif ras sw_init with oth
drm/amdgpu: Rework pcie_bif ras sw_init
pcie_bif ras blocks needs to be initialized as early
as possible to handle fatal error detected in hw_init
phase. also align the pcie_bif ras sw_init with other
ras blocks
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Stanley Yang <[email protected]>
Reviewed-by: Tao Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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| #
0d09a60e |
| 04-Apr-2022 |
Stanley.Yang <[email protected]> |
drm/amdgpu: add nbio v4_3_0 ip block v2
This adds nbio v4_3_0 ip block support
Changed from v1:
use WREG32_SOC15/RREG32_SOC15 instead of
WREG32_PCIE/RREG32_PCIE
remove the programming of PCIE_CONFI
drm/amdgpu: add nbio v4_3_0 ip block v2
This adds nbio v4_3_0 ip block support
Changed from v1:
use WREG32_SOC15/RREG32_SOC15 instead of
WREG32_PCIE/RREG32_PCIE
remove the programming of PCIE_CONFIG_CNTL
Signed-off-by: Stanley.Yang <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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Revision tags: v5.17, v5.17-rc8, v5.17-rc7, v5.17-rc6, v5.17-rc5, v5.17-rc4, v5.17-rc3, v5.17-rc2, v5.17-rc1, v5.16 |
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| #
fb1d6835 |
| 08-Jan-2022 |
Hawking Zhang <[email protected]> |
drm/amdgpu: add nbio callback to query rom offset
Add nbio callback func used to query rom offset.
Used to query the rom offset for fetching the vbios.
Acked-by: Christian König <christian.koenig@a
drm/amdgpu: add nbio callback to query rom offset
Add nbio callback func used to query rom offset.
Used to query the rom offset for fetching the vbios.
Acked-by: Christian König <[email protected]>
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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| #
25faeddc |
| 25-Mar-2022 |
Evan Quan <[email protected]> |
drm/amdgpu: expand cg_flags from u32 to u64
With this, we can support more CG flags.
Signed-off-by: Evan Quan <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Reviewed-by: Haw
drm/amdgpu: expand cg_flags from u32 to u64
With this, we can support more CG flags.
Signed-off-by: Evan Quan <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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| #
f578a37d |
| 14-Feb-2022 |
yipechai <[email protected]> |
drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in nbio ras block
Remove redundant calls of amdgpu_ras_block_late_fini in nbio ras block.
Signed-off-by: yipechai <[email protected]
drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in nbio ras block
Remove redundant calls of amdgpu_ras_block_late_fini in nbio ras block.
Signed-off-by: yipechai <[email protected]>
Reviewed-by: Tao Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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| #
01d468d9 |
| 17-Feb-2022 |
yipechai <[email protected]> |
drm/amdgpu: Modify .ras_fini function pointer parameter
Modify .ras_fini function pointer parameter so that
we can remove redundant intermediate calls in some
ras blocks.
Signed-off-by: yipechai <Y
drm/amdgpu: Modify .ras_fini function pointer parameter
Modify .ras_fini function pointer parameter so that
we can remove redundant intermediate calls in some
ras blocks.
Signed-off-by: yipechai <[email protected]>
Reviewed-by: Tao Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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| #
4e9b1fa5 |
| 14-Feb-2022 |
yipechai <[email protected]> |
drm/amdgpu: Modify .ras_late_init function pointer parameter
Modify .ras_late_init function pointer parameter so that
it can remove redundant intermediate calls in some ras blocks.
Signed-off-by: y
drm/amdgpu: Modify .ras_late_init function pointer parameter
Modify .ras_late_init function pointer parameter so that
it can remove redundant intermediate calls in some ras blocks.
Signed-off-by: yipechai <[email protected]>
Reviewed-by: Tao Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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| #
2e54fe5d |
| 05-Jan-2022 |
yipechai <[email protected]> |
drm/amdgpu: Modify nbio block to fit for the unified ras block data and ops
1.Modify nbio block to fit for the unified ras block data and ops.
2.Change amdgpu_nbio_ras_funcs to amdgpu_nbio_ras, and
drm/amdgpu: Modify nbio block to fit for the unified ras block data and ops
1.Modify nbio block to fit for the unified ras block data and ops.
2.Change amdgpu_nbio_ras_funcs to amdgpu_nbio_ras, and the corresponding variable name remove _funcs suffix.
3.Remove the const flag of mmhub ras variable so that nbio ras block can be able to be inserted into amdgpu device ras block link list.
4.Invoke amdgpu_ras_register_ras_block function to register nbio ras block into amdgpu device ras block link list.
5.Remove the redundant code about nbio in amdgpu_ras.c after using the unified ras block.
Signed-off-by: yipechai <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: John Clements <[email protected]>
Reviewed-by: Tao Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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Revision tags: v5.16-rc8, v5.16-rc7, v5.16-rc6, v5.16-rc5, v5.16-rc4, v5.16-rc3, v5.16-rc2, v5.16-rc1, v5.15, v5.15-rc7, v5.15-rc6, v5.15-rc5, v5.15-rc4, v5.15-rc3, v5.15-rc2, v5.15-rc1, v5.14, v5.14-rc7, v5.14-rc6, v5.14-rc5, v5.14-rc4, v5.14-rc3 |
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| #
1bece222 |
| 20-Jul-2021 |
Chengzhe Liu <[email protected]> |
drm/amdgpu: Clear doorbell interrupt status for Sienna Cichlid
On Sienna Cichlid, in pass-through mode, if we unload the driver in BACO
mode(RTPM), then the kernel would receive thousands of interru
drm/amdgpu: Clear doorbell interrupt status for Sienna Cichlid
On Sienna Cichlid, in pass-through mode, if we unload the driver in BACO
mode(RTPM), then the kernel would receive thousands of interrupts.
That's because there is doorbell monitor interrupt on BIF, so KVM keeps
injecting interrupts to the guest VM. So we should clear the doorbell
interrupt status after BACO exit.
v2: Modify coding style and commit message
Signed-off-by: Chengzhe Liu <[email protected]>
Reviewed-by: Luben Tuikov <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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Revision tags: v5.14-rc2, v5.14-rc1, v5.13, v5.13-rc7, v5.13-rc6, v5.13-rc5, v5.13-rc4 |
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| #
adcf949e |
| 25-May-2021 |
Evan Quan <[email protected]> |
drm/amdgpu: fix the hang caused by PCIe link width switch
SMU had set all the necessary fields for a link width switch
but the width switch wasn't occurring because the link was idle
in the L1 state
drm/amdgpu: fix the hang caused by PCIe link width switch
SMU had set all the necessary fields for a link width switch
but the width switch wasn't occurring because the link was idle
in the L1 state. Setting LC_L1_RECONFIG_EN=0x1 will allow width
switches to also be initiated while in L1 instead of waiting until
the link is back in L0.
Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]
show more ...
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| #
5a5da8ae |
| 25-May-2021 |
Evan Quan <[email protected]> |
drm/amdgpu: fix NAK-G generation during PCI-e link width switch
A lot of NAK-G being generated when link widht switching is happening.
WA for this issue is to program the SPC to 4 symbols per clock
drm/amdgpu: fix NAK-G generation during PCI-e link width switch
A lot of NAK-G being generated when link widht switching is happening.
WA for this issue is to program the SPC to 4 symbols per clock during
bootup when the native PCIE width is x4.
Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]
show more ...
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Revision tags: v5.13-rc3, v5.13-rc2, v5.13-rc1, v5.12, v5.12-rc8, v5.12-rc7, v5.12-rc6 |
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| #
6e36f231 |
| 02-Apr-2021 |
Hawking Zhang <[email protected]> |
drm/amdgpu: split nbio callbacks into ras and non-ras ones
nbio ras is not managed by gpu driver when gpu is
connected to cpu through xgmi. split nbio callbacks
into ras and non-ras ones so gpu driv
drm/amdgpu: split nbio callbacks into ras and non-ras ones
nbio ras is not managed by gpu driver when gpu is
connected to cpu through xgmi. split nbio callbacks
into ras and non-ras ones so gpu driver only
initializes nbio ras callbacks when it manages
nbio ras.
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Dennis Li <[email protected]>
Reviewed-by: John Clements <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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Revision tags: v5.12-rc5, v5.12-rc4, v5.12-rc3, v5.12-rc2, v5.12-rc1, v5.12-rc1-dontuse, v5.11, v5.11-rc7 |
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| #
e1edaeaf |
| 01-Feb-2021 |
Likun Gao <[email protected]> |
drm/amdgpu: support ASPM for some specific ASIC
Support to program ASPM and LTR for Sienna Cichlid and forward ASIC.
Disable ASPM for Sienna Cichlid and forward ASIC by default.
Signed-off-by: Liku
drm/amdgpu: support ASPM for some specific ASIC
Support to program ASPM and LTR for Sienna Cichlid and forward ASIC.
Disable ASPM for Sienna Cichlid and forward ASIC by default.
Signed-off-by: Likun Gao <[email protected]>
Reviewed-by: Kenneth Feng <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
show more ...
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