| e32634f4 | 26-Mar-2024 |
Baruch Siach <[email protected]> |
dma: dw-axi-dmac: support per channel interrupt
Hardware might not support a single combined interrupt that covers all channels. In that case we have to deal with interrupt per channel. Add support
dma: dw-axi-dmac: support per channel interrupt
Hardware might not support a single combined interrupt that covers all channels. In that case we have to deal with interrupt per channel. Add support for that configuration.
Signed-off-by: Baruch Siach <[email protected]> Link: https://lore.kernel.org/r/ebab52e886ef1adc3c40e636aeb1ba3adfe2e578.1711453387.git.baruchs-c@neureality.ai Signed-off-by: Vinod Koul <[email protected]>
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| 333e11bf | 27-Mar-2024 |
Joao Pinto <[email protected]> |
Avoid hw_desc array overrun in dw-axi-dmac
I have a use case where nr_buffers = 3 and in which each descriptor is composed by 3 segments, resulting in the DMA channel descs_allocated to be 9. Since
Avoid hw_desc array overrun in dw-axi-dmac
I have a use case where nr_buffers = 3 and in which each descriptor is composed by 3 segments, resulting in the DMA channel descs_allocated to be 9. Since axi_desc_put() handles the hw_desc considering the descs_allocated, this scenario would result in a kernel panic (hw_desc array will be overrun).
To fix this, the proposal is to add a new member to the axi_dma_desc structure, where we keep the number of allocated hw_descs (axi_desc_alloc()) and use it in axi_desc_put() to handle the hw_desc array correctly.
Additionally I propose to remove the axi_chan_start_first_queued() call after completing the transfer, since it was identified that unbalance can occur (started descriptors can be interrupted and transfer ignored due to DMA channel not being enabled).
Signed-off-by: Joao Pinto <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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| ce62432c | 22-Mar-2023 |
Walker Chen <[email protected]> |
dmaengine: dw-axi-dmac: Increase polling time to DMA transmission completion status
The bit DMAC_CHEN[0] is automatically cleared by hardware to disable the channel after the last AMBA transfer of t
dmaengine: dw-axi-dmac: Increase polling time to DMA transmission completion status
The bit DMAC_CHEN[0] is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer. This time requires at least 40 milliseconds on JH7110 SoC, otherwise an error message 'failed to stop' will be reported.
Signed-off-by: Walker Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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| be4d46ed | 27-Jan-2023 |
Kees Cook <[email protected]> |
dmaengine: dw-axi-dmac: Do not dereference NULL structure
If "vdesc" is NULL, it cannot be used with vd_to_axi_desc(). Leave "bytes" unchanged at 0. Seen under GCC 13 with -Warray-bounds:
../driver
dmaengine: dw-axi-dmac: Do not dereference NULL structure
If "vdesc" is NULL, it cannot be used with vd_to_axi_desc(). Leave "bytes" unchanged at 0. Seen under GCC 13 with -Warray-bounds:
../drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: In function 'dma_chan_tx_status': ../drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:329:46: warning: array subscript 0 is outside array bounds of 'struct virt_dma_desc[46116860184273879]' [-Warray-bounds=] 329 | bytes = vd_to_axi_desc(vdesc)->length; | ^~
Fixes: 8e55444da65c ("dmaengine: dw-axi-dmac: Support burst residue granularity") Cc: Eugeniy Paltsev <[email protected]> Cc: Vinod Koul <[email protected]> Cc: [email protected] Signed-off-by: Kees Cook <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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/linux-6.15/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/altr,msgdma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/apple,admac.yaml/linux-6.15/Documentation/devicetree/bindings/dma/arm-pl08x.yaml/linux-6.15/Documentation/devicetree/bindings/dma/dma-controller.yaml/linux-6.15/Documentation/devicetree/bindings/dma/dma-router.yaml/linux-6.15/Documentation/devicetree/bindings/dma/fsl,edma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/ingenic,dma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/intel,ldma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/owl-dma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/qcom,gpi.yaml/linux-6.15/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml/linux-6.15/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml/linux-6.15/Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml/linux-6.15/Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml/linux-6.15/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml/linux-6.15/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml/linux-6.15/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml/linux-6.15/Documentation/devicetree/bindings/dma/socionext,uniphier-xdmac.yaml/linux-6.15/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml/linux-6.15/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml/linux-6.15/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml/linux-6.15/MAINTAINERS/linux-6.15/drivers/dma/Kconfig/linux-6.15/drivers/dma/dmaengine.cdw-axi-dmac-platform.c/linux-6.15/drivers/dma/idxd/device.c/linux-6.15/drivers/dma/idxd/init.c/linux-6.15/drivers/dma/sf-pdma/sf-pdma.c/linux-6.15/drivers/dma/sf-pdma/sf-pdma.h/linux-6.15/drivers/dma/xilinx/Makefile/linux-6.15/drivers/dma/xilinx/xdma-regs.h/linux-6.15/drivers/dma/xilinx/xdma.c/linux-6.15/include/linux/dma/amd_xdma.h/linux-6.15/include/linux/dmaengine.h/linux-6.15/include/linux/platform_data/amd_xdma.h |
| 2d0f07f8 | 01-Oct-2021 |
Pandith N <[email protected]> |
dmaengine: dw-axi-dmac: set coherent mask
Add support for setting dma coherent mask, dma mask is set to 64 bit
Signed-off-by: Pandith N <[email protected]> Reviewed-by: Andy Shevchenko <andriy.sh
dmaengine: dw-axi-dmac: set coherent mask
Add support for setting dma coherent mask, dma mask is set to 64 bit
Signed-off-by: Pandith N <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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| 93a7d32e | 01-Oct-2021 |
Pandith N <[email protected]> |
dmaengine: dw-axi-dmac: Hardware handshake configuration
Added hardware handshake selection in channel config, for mem2per and per2mem case. The peripheral specific handshake interface needs to be p
dmaengine: dw-axi-dmac: Hardware handshake configuration
Added hardware handshake selection in channel config, for mem2per and per2mem case. The peripheral specific handshake interface needs to be programmed in src_per, dst_per bits of CHx_CFG register.
Signed-off-by: Pandith N <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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| c454d16a | 02-Aug-2021 |
Pandith N <[email protected]> |
dmaengine: dw-axi-dmac: Burst length settings
Burst length, DMA HW capability set in dt-binding is now used in driver.
Signed-off-by: Pandith N <[email protected]> Tested-by: Pan Kris <kris.pan@i
dmaengine: dw-axi-dmac: Burst length settings
Burst length, DMA HW capability set in dt-binding is now used in driver.
Signed-off-by: Pandith N <[email protected]> Tested-by: Pan Kris <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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| f95f3b53 | 02-Aug-2021 |
Pandith N <[email protected]> |
dmaengine: dw-axi-dmac: support parallel memory <--> peripheral transfers
Added support for multiple DMA_MEM_TO_DEV, DMA_DEV_TO_MEM transfers in parallel. This is required for peripherals using DMA
dmaengine: dw-axi-dmac: support parallel memory <--> peripheral transfers
Added support for multiple DMA_MEM_TO_DEV, DMA_DEV_TO_MEM transfers in parallel. This is required for peripherals using DMA for transmit and receive operations at the same time. APB slot number needs to be programmed in channel hardware handshaking interface
Signed-off-by: Pandith N <[email protected]> Tested-by: Pan Kris <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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