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Revision tags: v6.15, v6.15-rc7, v6.15-rc6, v6.15-rc5, v6.15-rc4, v6.15-rc3, v6.15-rc2, v6.15-rc1, v6.14, v6.14-rc7, v6.14-rc6, v6.14-rc5, v6.14-rc4, v6.14-rc3, v6.14-rc2, v6.14-rc1, v6.13, v6.13-rc7, v6.13-rc6, v6.13-rc5, v6.13-rc4 |
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16479389 |
| 18-Dec-2024 |
Michael Ellerman <[email protected]> |
cpufreq: ppc_cbe: Remove powerpc Cell driver
This driver can no longer be built since support for IBM Cell Blades was removed, in particular CBE_RAS.
Remove the driver.
Signed-off-by: Michael Elle
cpufreq: ppc_cbe: Remove powerpc Cell driver
This driver can no longer be built since support for IBM Cell Blades was removed, in particular CBE_RAS.
Remove the driver.
Signed-off-by: Michael Ellerman <[email protected]> Signed-off-by: Madhavan Srinivasan <[email protected]> Link: https://patch.msgid.link/[email protected]
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84cf9e54 |
| 09-Jan-2025 |
Christian Marangi <[email protected]> |
cpufreq: airoha: Add EN7581 CPUFreq SMCCC driver
Add simple CPU Freq driver for Airoha EN7581 SoC that control CPU frequency scaling with SMC APIs and register a generic "cpufreq-dt" device.
All CP
cpufreq: airoha: Add EN7581 CPUFreq SMCCC driver
Add simple CPU Freq driver for Airoha EN7581 SoC that control CPU frequency scaling with SMC APIs and register a generic "cpufreq-dt" device.
All CPU share the same frequency and can't be controlled independently. CPU frequency is controlled by the attached PM domain.
Add SoC compatible to cpufreq-dt-plat block list as a dedicated cpufreq driver is needed with OPP v2 nodes declared in DTS.
Signed-off-by: Christian Marangi <[email protected]> Signed-off-by: Viresh Kumar <[email protected]>
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Revision tags: v6.13-rc3, v6.13-rc2, v6.13-rc1, v6.12 |
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fae2987e |
| 12-Nov-2024 |
Michael Ellerman <[email protected]> |
cpufreq: maple: Remove maple driver
This driver is no longer buildable since the PPC_MAPLE platform was removed, see commit 62f8f307c80e ("powerpc/64: Remove maple platform").
Remove the driver.
N
cpufreq: maple: Remove maple driver
This driver is no longer buildable since the PPC_MAPLE platform was removed, see commit 62f8f307c80e ("powerpc/64: Remove maple platform").
Remove the driver.
Note that the comment in the driver says it supports "SMU & 970FX based G5 Macs", but that's not true, that comment was copied from pmac64-cpufreq.c, which still exists and continues to support those machines.
Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://patch.msgid.link/[email protected]
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Revision tags: v6.12-rc7, v6.12-rc6, v6.12-rc5, v6.12-rc4, v6.12-rc3, v6.12-rc2, v6.12-rc1 |
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4fd06a53 |
| 19-Sep-2024 |
David Dai <[email protected]> |
cpufreq: add virtual-cpufreq driver
Introduce a virtualized cpufreq driver for guest kernels to improve performance and power of workloads within VMs.
This driver does two main things:
1. Sends th
cpufreq: add virtual-cpufreq driver
Introduce a virtualized cpufreq driver for guest kernels to improve performance and power of workloads within VMs.
This driver does two main things:
1. Sends the frequency of vCPUs as a hint to the host. The host uses the hint to schedule the vCPU threads and decide physical CPU frequency.
2. If a VM does not support a virtualized FIE(like AMUs), it queries the host CPU frequency by reading a MMIO region of a virtual cpufreq device to update the guest's frequency scaling factor periodically. This enables accurate Per-Entity Load Tracking for tasks running in the guest.
Co-developed-by: Saravana Kannan <[email protected]> Signed-off-by: Saravana Kannan <[email protected]> Signed-off-by: David Dai <[email protected]> Signed-off-by: Viresh Kumar <[email protected]>
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Revision tags: v6.11, v6.11-rc7, v6.11-rc6, v6.11-rc5, v6.11-rc4, v6.11-rc3, v6.11-rc2, v6.11-rc1, v6.10, v6.10-rc7 |
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ccf51454 |
| 05-Jul-2024 |
Huacai Chen <[email protected]> |
cpufreq: Add Loongson-3 CPUFreq driver support
Some of LoongArch processors (Loongson-3 series) support DVFS, their IOCSR.FEATURES has IOCSRF_FREQSCALE set. And they has a micro-core in the package
cpufreq: Add Loongson-3 CPUFreq driver support
Some of LoongArch processors (Loongson-3 series) support DVFS, their IOCSR.FEATURES has IOCSRF_FREQSCALE set. And they has a micro-core in the package called SMC (System Management Controller), which can be used to detect temperature, control fans, scale frequency and voltage, etc.
The Loongson-3 CPUFreq driver is very simple now, it communicate with SMC, get DVFS info, set target frequency from CPUFreq core, and so on.
There is a command list to interact with SMC, widely-used commands in the CPUFreq driver include:
CMD_GET_VERSION: Get SMC firmware version.
CMD_GET_FEATURE: Get enabled SMC features.
CMD_SET_FEATURE: Enable SMC features, such as basic DVFS, BOOST.
CMD_GET_FREQ_LEVEL_NUM: Get the number of all frequency levels.
CMD_GET_FREQ_BOOST_LEVEL: Get the first boost frequency level.
CMD_GET_FREQ_LEVEL_INFO: Get the detail info of a frequency level.
CMD_GET_FREQ_INFO: Get the current frequency.
CMD_SET_FREQ_INFO: Set the target frequency.
In future we will add automatic frequency scaling, which is similar to Intel's HWP (HardWare P-State).
Signed-off-by: Binbin Zhou <[email protected]> Signed-off-by: Huacai Chen <[email protected]> [ Viresh: Minor formatting cleanups, change return type of exit() to void and use devm_mutex_init() ] Signed-off-by: Viresh Kumar <[email protected]>
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Revision tags: v6.10-rc6, v6.10-rc5, v6.10-rc4, v6.10-rc3, v6.10-rc2, v6.10-rc1, v6.9, v6.9-rc7, v6.9-rc6, v6.9-rc5, v6.9-rc4, v6.9-rc3, v6.9-rc2, v6.9-rc1, v6.8, v6.8-rc7, v6.8-rc6, v6.8-rc5, v6.8-rc4, v6.8-rc3, v6.8-rc2, v6.8-rc1, v6.7, v6.7-rc8, v6.7-rc7, v6.7-rc6, v6.7-rc5, v6.7-rc4, v6.7-rc3, v6.7-rc2, v6.7-rc1, v6.6, v6.6-rc7, v6.6-rc6, v6.6-rc5, v6.6-rc4, v6.6-rc3, v6.6-rc2, v6.6-rc1, v6.5, v6.5-rc7, v6.5-rc6, v6.5-rc5, v6.5-rc4, v6.5-rc3, v6.5-rc2, v6.5-rc1, v6.4, v6.4-rc7, v6.4-rc6, v6.4-rc5, v6.4-rc4, v6.4-rc3, v6.4-rc2, v6.4-rc1, v6.3, v6.3-rc7, v6.3-rc6, v6.3-rc5, v6.3-rc4, v6.3-rc3, v6.3-rc2, v6.3-rc1, v6.2, v6.2-rc8, v6.2-rc7, v6.2-rc6, v6.2-rc5, v6.2-rc4, v6.2-rc3, v6.2-rc2, v6.2-rc1, v6.1, v6.1-rc8, v6.1-rc7, v6.1-rc6, v6.1-rc5, v6.1-rc4, v6.1-rc3, v6.1-rc2 |
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cf8e8658 |
| 20-Oct-2022 |
Ard Biesheuvel <[email protected]> |
arch: Remove Itanium (IA-64) architecture
The Itanium architecture is obsolete, and an informal survey [0] reveals that any residual use of Itanium hardware in production is mostly HP-UX or OpenVMS
arch: Remove Itanium (IA-64) architecture
The Itanium architecture is obsolete, and an informal survey [0] reveals that any residual use of Itanium hardware in production is mostly HP-UX or OpenVMS based. The use of Linux on Itanium appears to be limited to enthusiasts that occasionally boot a fresh Linux kernel to see whether things are still working as intended, and perhaps to churn out some distro packages that are rarely used in practice.
None of the original companies behind Itanium still produce or support any hardware or software for the architecture, and it is listed as 'Orphaned' in the MAINTAINERS file, as apparently, none of the engineers that contributed on behalf of those companies (nor anyone else, for that matter) have been willing to support or maintain the architecture upstream or even be responsible for applying the odd fix. The Intel firmware team removed all IA-64 support from the Tianocore/EDK2 reference implementation of EFI in 2018. (Itanium is the original architecture for which EFI was developed, and the way Linux supports it deviates significantly from other architectures.) Some distros, such as Debian and Gentoo, still maintain [unofficial] ia64 ports, but many have dropped support years ago.
While the argument is being made [1] that there is a 'for the common good' angle to being able to build and run existing projects such as the Grid Community Toolkit [2] on Itanium for interoperability testing, the fact remains that none of those projects are known to be deployed on Linux/ia64, and very few people actually have access to such a system in the first place. Even if there were ways imaginable in which Linux/ia64 could be put to good use today, what matters is whether anyone is actually doing that, and this does not appear to be the case.
There are no emulators widely available, and so boot testing Itanium is generally infeasible for ordinary contributors. GCC still supports IA-64 but its compile farm [3] no longer has any IA-64 machines. GLIBC would like to get rid of IA-64 [4] too because it would permit some overdue code cleanups. In summary, the benefits to the ecosystem of having IA-64 be part of it are mostly theoretical, whereas the maintenance overhead of keeping it supported is real.
So let's rip off the band aid, and remove the IA-64 arch code entirely. This follows the timeline proposed by the Debian/ia64 maintainer [5], which removes support in a controlled manner, leaving IA-64 in a known good state in the most recent LTS release. Other projects will follow once the kernel support is removed.
[0] https://lore.kernel.org/all/CAMj1kXFCMh_578jniKpUtx_j8ByHnt=s7S+yQ+vGbKt9ud7+kQ@mail.gmail.com/ [1] https://lore.kernel.org/all/[email protected]/ [2] https://gridcf.org/gct-docs/latest/index.html [3] https://cfarm.tetaneutral.net/machines/list/ [4] https://lore.kernel.org/all/[email protected]/ [5] https://lore.kernel.org/all/ff58a3e76e5102c94bb5946d99187b358def688a.camel@physik.fu-berlin.de/
Acked-by: Tony Luck <[email protected]> Signed-off-by: Ard Biesheuvel <[email protected]>
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9a55ab6f |
| 12-Jan-2023 |
Keguang Zhang <[email protected]> |
cpufreq: loongson1: Delete obsolete driver
The generic DT based cpufreq driver works for Loongson-1, so delete the old custom driver.
Signed-off-by: Keguang Zhang <[email protected]> Signed-o
cpufreq: loongson1: Delete obsolete driver
The generic DT based cpufreq driver works for Loongson-1, so delete the old custom driver.
Signed-off-by: Keguang Zhang <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
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Revision tags: v6.1-rc1, v6.0 |
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014e79d7 |
| 30-Sep-2022 |
Arnd Bergmann <[email protected]> |
cpufreq: remove s3c24xx drivers
All s3c24xx platforms were removed, so these five drivers are all obsolete now.
Reviewed-by: Krzysztof Kozlowski <[email protected]> Acked-by: Viresh Ku
cpufreq: remove s3c24xx drivers
All s3c24xx platforms were removed, so these five drivers are all obsolete now.
Reviewed-by: Krzysztof Kozlowski <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
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349619f0 |
| 30-Sep-2022 |
Arnd Bergmann <[email protected]> |
cpufreq: remove sa1100 driver
The sa11xx platform has two cpufreq drivers, one for the older StrongARM1100 SoC, and a second one for StrongARM1110. After the removal of most SA1100 based machines, t
cpufreq: remove sa1100 driver
The sa11xx platform has two cpufreq drivers, one for the older StrongARM1100 SoC, and a second one for StrongARM1110. After the removal of most SA1100 based machines, this driver is unused, and only the sa1110-cpufreq driver remains.
Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
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6286bbb4 |
| 28-Nov-2022 |
Hector Martin <[email protected]> |
cpufreq: apple-soc: Add new driver to control Apple SoC CPU P-states
This driver implements CPU frequency scaling for Apple Silicon SoCs, including M1 (t8103), M1 Max/Pro/Ultra (t600x), and M2 (t811
cpufreq: apple-soc: Add new driver to control Apple SoC CPU P-states
This driver implements CPU frequency scaling for Apple Silicon SoCs, including M1 (t8103), M1 Max/Pro/Ultra (t600x), and M2 (t8112).
Each CPU cluster has its own register set, and frequency management is fully automated by the hardware; the driver only has to write one register. There is boost frequency support, but the hardware will only allow their use if only a subset of cores in a cluster are in non-deep-idle. Since we don't support deep idle yet, these frequencies are not achievable, but the driver supports them. They will remain disabled in the device tree until deep idle is implemented, to avoid confusing users.
This driver does not yet implement the memory controller performance state tuning that usually accompanies higher CPU p-states. This will be done in a future patch.
Acked-by: Marc Zyngier <[email protected]> Signed-off-by: Hector Martin <[email protected]> Signed-off-by: Viresh Kumar <[email protected]>
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Revision tags: v6.0-rc7, v6.0-rc6, v6.0-rc5, v6.0-rc4, v6.0-rc3, v6.0-rc2 |
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14eb1c96 |
| 17-Aug-2022 |
Meng Li <[email protected]> |
cpufreq: amd-pstate: Add test module for amd-pstate driver
Add amd-pstate-ut test module, this module is used by kselftest to unit test amd-pstate functionality. This module will be expected by some
cpufreq: amd-pstate: Add test module for amd-pstate driver
Add amd-pstate-ut test module, this module is used by kselftest to unit test amd-pstate functionality. This module will be expected by some of selftests to be present and loaded.
Signed-off-by: Meng Li <[email protected]> Acked-by: Huang Rui <[email protected]> Reviewed-by: Shuah Khan <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
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Revision tags: v6.0-rc1, v5.19, v5.19-rc8, v5.19-rc7, v5.19-rc6, v5.19-rc5, v5.19-rc4, v5.19-rc3, v5.19-rc2, v5.19-rc1, v5.18, v5.18-rc7, v5.18-rc6, v5.18-rc5, v5.18-rc4, v5.18-rc3, v5.18-rc2, v5.18-rc1, v5.17, v5.17-rc8, v5.17-rc7, v5.17-rc6, v5.17-rc5, v5.17-rc4, v5.17-rc3, v5.17-rc2, v5.17-rc1, v5.16, v5.16-rc8, v5.16-rc7 |
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60e10f89 |
| 24-Dec-2021 |
Huang Rui <[email protected]> |
cpufreq: amd-pstate: Add trace for AMD P-State module
Add trace event to monitor the performance value changes which is controlled by cpu governors.
Signed-off-by: Huang Rui <[email protected]> Sig
cpufreq: amd-pstate: Add trace for AMD P-State module
Add trace event to monitor the performance value changes which is controlled by cpu governors.
Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
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ec437d71 |
| 24-Dec-2021 |
Huang Rui <[email protected]> |
cpufreq: amd-pstate: Introduce a new AMD P-State driver to support future processors
AMD P-State is the AMD CPU performance scaling driver that introduces a new CPU frequency control mechanism on AM
cpufreq: amd-pstate: Introduce a new AMD P-State driver to support future processors
AMD P-State is the AMD CPU performance scaling driver that introduces a new CPU frequency control mechanism on AMD Zen based CPU series in Linux kernel. The new mechanism is based on Collaborative processor performance control (CPPC) which is finer grain frequency management than legacy ACPI hardware P-States. Current AMD CPU platforms are using the ACPI P-states driver to manage CPU frequency and clocks with switching only in 3 P-states. AMD P-State is to replace the ACPI P-states controls, allows a flexible, low-latency interface for the Linux kernel to directly communicate the performance hints to hardware.
AMD P-State leverages the Linux kernel governors such as *schedutil*, *ondemand*, etc. to manage the performance hints which are provided by CPPC hardware functionality. The first version for AMD P-State is to support one of the Zen3 processors, and we will support more in future after we verify the hardware and SBIOS functionalities.
There are two types of hardware implementations for AMD P-State: one is full MSR support and another is shared memory support. It can use X86_FEATURE_CPPC feature flag to distinguish the different types.
Using the new AMD P-State method + kernel governors (*schedutil*, *ondemand*, ...) to manage the frequency update is the most appropriate bridge between AMD Zen based hardware processor and Linux kernel, the processor is able to adjust to the most efficiency frequency according to the kernel scheduler loading.
Please check the detailed CPU feature and MSR register description in Processor Programming Reference (PPR) for AMD Family 19h Model 51h, Revision A1 Processors:
https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip
Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
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Revision tags: v5.16-rc6, v5.16-rc5, v5.16-rc4, v5.16-rc3, v5.16-rc2, v5.16-rc1, v5.15, v5.15-rc7, v5.15-rc6, v5.15-rc5, v5.15-rc4, v5.15-rc3, v5.15-rc2, v5.15-rc1 |
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| #
4855e26b |
| 03-Sep-2021 |
Hector.Yuan <[email protected]> |
cpufreq: mediatek-hw: Add support for CPUFREQ HW
Introduce cpufreq HW driver which can support CPU frequency adjust in MT6779 platform.
Signed-off-by: Hector.Yuan <[email protected]> [ Vires
cpufreq: mediatek-hw: Add support for CPUFREQ HW
Introduce cpufreq HW driver which can support CPU frequency adjust in MT6779 platform.
Signed-off-by: Hector.Yuan <[email protected]> [ Viresh: Massaged the patch and cleaned some stuff. ] Signed-off-by: Viresh Kumar <[email protected]>
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Revision tags: v5.14, v5.14-rc7, v5.14-rc6, v5.14-rc5, v5.14-rc4, v5.14-rc3, v5.14-rc2, v5.14-rc1, v5.13, v5.13-rc7, v5.13-rc6, v5.13-rc5, v5.13-rc4, v5.13-rc3, v5.13-rc2, v5.13-rc1, v5.12, v5.12-rc8, v5.12-rc7, v5.12-rc6, v5.12-rc5, v5.12-rc4, v5.12-rc3, v5.12-rc2, v5.12-rc1, v5.12-rc1-dontuse, v5.11 |
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| #
73f70d6c |
| 11-Feb-2021 |
Andy Shevchenko <[email protected]> |
cpufreq: sfi-cpufreq: Remove driver for deprecated firmware
SFI-based platforms are gone. So does this driver.
Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Linus Wal
cpufreq: sfi-cpufreq: Remove driver for deprecated firmware
SFI-based platforms are gone. So does this driver.
Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
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Revision tags: v5.11-rc7, v5.11-rc6, v5.11-rc5 |
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7114ebff |
| 20-Jan-2021 |
Arnd Bergmann <[email protected]> |
cpufreq: remove tango driver
The tango platform is getting removed, so the driver is no longer needed.
Cc: Marc Gonzalez <[email protected]> Cc: Mans Rullgard <[email protected]> Signed-off-by:
cpufreq: remove tango driver
The tango platform is getting removed, so the driver is no longer needed.
Cc: Marc Gonzalez <[email protected]> Cc: Mans Rullgard <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]> [ Viresh: Update cpufreq-dt-platdev.c as well ] Signed-off-by: Viresh Kumar <[email protected]>
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Revision tags: v5.11-rc4, v5.11-rc3, v5.11-rc2, v5.11-rc1, v5.10, v5.10-rc7, v5.10-rc6, v5.10-rc5, v5.10-rc4, v5.10-rc3, v5.10-rc2, v5.10-rc1, v5.9, v5.9-rc8, v5.9-rc7, v5.9-rc6, v5.9-rc5, v5.9-rc4, v5.9-rc3, v5.9-rc2, v5.9-rc1, v5.8, v5.8-rc7, v5.8-rc6 |
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df320f89 |
| 16-Jul-2020 |
Sumit Gupta <[email protected]> |
cpufreq: Add Tegra194 cpufreq driver
Add support for CPU frequency scaling on Tegra194. The frequency of each core can be adjusted by writing a clock divisor value to a MSR on the core. The range of
cpufreq: Add Tegra194 cpufreq driver
Add support for CPU frequency scaling on Tegra194. The frequency of each core can be adjusted by writing a clock divisor value to a MSR on the core. The range of valid divisors is queried from the BPMP.
Signed-off-by: Mikko Perttunen <[email protected]> Signed-off-by: Sumit Gupta <[email protected]> Signed-off-by: Viresh Kumar <[email protected]>
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Revision tags: v5.8-rc5, v5.8-rc4, v5.8-rc3, v5.8-rc2, v5.8-rc1 |
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5853d602 |
| 10-Jun-2020 |
Mike Rapoport <[email protected]> |
cpufreq: remove unicore32 driver
The unicore32 port is removed from the kernel. There is no point to keep stale cpufreq driver for this architecture.
Signed-off-by: Mike Rapoport <[email protected]
cpufreq: remove unicore32 driver
The unicore32 port is removed from the kernel. There is no point to keep stale cpufreq driver for this architecture.
Signed-off-by: Mike Rapoport <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Acked-by: Guenter Roeck <[email protected]>
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Revision tags: v5.7, v5.7-rc7, v5.7-rc6, v5.7-rc5, v5.7-rc4, v5.7-rc3, v5.7-rc2, v5.7-rc1, v5.6, v5.6-rc7, v5.6-rc6, v5.6-rc5, v5.6-rc4, v5.6-rc3, v5.6-rc2, v5.6-rc1, v5.5, v5.5-rc7, v5.5-rc6, v5.5-rc5, v5.5-rc4, v5.5-rc3, v5.5-rc2, v5.5-rc1, v5.4, v5.4-rc8, v5.4-rc7, v5.4-rc6, v5.4-rc5 |
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a0f950d3 |
| 21-Oct-2019 |
Sudeep Holla <[email protected]> |
cpufreq: merge arm_big_little and vexpress-spc
arm_big_little cpufreq driver was designed as a generic big little driver that could be used by any platform and make use of bL switcher. Over years al
cpufreq: merge arm_big_little and vexpress-spc
arm_big_little cpufreq driver was designed as a generic big little driver that could be used by any platform and make use of bL switcher. Over years alternate solutions have been designed and merged to deal with bL/HMP systems like EAS.
Also since no other driver made use of generic arm_big_little cpufreq driver except Vexpress SPC, we can merge them together as vexpress-spc driver used only on Vexpress TC2(CA15_CA7) platform.
Acked-by: Nicolas Pitre <[email protected]> Signed-off-by: Sudeep Holla <[email protected]> Signed-off-by: Viresh Kumar <[email protected]>
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Revision tags: v5.4-rc4, v5.4-rc3, v5.4-rc2, v5.4-rc1, v5.3, v5.3-rc8, v5.3-rc7, v5.3-rc6, v5.3-rc5, v5.3-rc4, v5.3-rc3, v5.3-rc2 |
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7d127095 |
| 25-Jul-2019 |
Sricharan R <[email protected]> |
cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
The kryo cpufreq driver reads the nvmem cell and uses that data to populate the opps. There are other qcom cpufreq s
cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
The kryo cpufreq driver reads the nvmem cell and uses that data to populate the opps. There are other qcom cpufreq socs like krait which does similar thing. Except for the interpretation of the read data, rest of the driver is same for both the cases. So pull the common things out for reuse.
Signed-off-by: Sricharan R <[email protected]> [[email protected]: split dt-binding into a separate patch and do not rename the compatible string. Update MAINTAINERS file.] Signed-off-by: Niklas Cassel <[email protected]> Reviewed-by: Ilia Lin <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Viresh Kumar <[email protected]>
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Revision tags: v5.3-rc1, v5.2, v5.2-rc7, v5.2-rc6, v5.2-rc5 |
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f328584f |
| 12-Jun-2019 |
Yangtao Li <[email protected]> |
cpufreq: Add sun50i nvmem based CPU scaling driver
For some SoCs, the CPU frequency subset and voltage value of each OPP varies based on the silicon variant in use. The sun50i-cpufreq-nvmem driver r
cpufreq: Add sun50i nvmem based CPU scaling driver
For some SoCs, the CPU frequency subset and voltage value of each OPP varies based on the silicon variant in use. The sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to provide the OPP framework with required information.
Signed-off-by: Yangtao Li <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Viresh Kumar <[email protected]>
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d3df18a9 |
| 12-Jun-2019 |
Nicolas Saenz Julienne <[email protected]> |
cpufreq: add driver for Raspberry Pi
Raspberry Pi's firmware offers and interface though which update it's performance requirements. It allows us to request for specific runtime frequencies, which t
cpufreq: add driver for Raspberry Pi
Raspberry Pi's firmware offers and interface though which update it's performance requirements. It allows us to request for specific runtime frequencies, which the firmware might or might not respect, depending on the firmware configuration and thermals.
As the maximum and minimum frequencies are configurable in the firmware there is no way to know in advance their values. So the Raspberry Pi cpufreq driver queries them, builds an opp frequency table to then launch cpufreq-dt.
Also, as the firmware interface might be configured as a module, making the cpu clock unavailable during init, this implements a full fledged driver, as opposed to most drivers registering cpufreq-dt, which only make use of an init routine.
Signed-off-by: Nicolas Saenz Julienne <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Acked-by: Stefan Wahren <[email protected]> Signed-off-by: Viresh Kumar <[email protected]>
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Revision tags: v5.2-rc4, v5.2-rc3, v5.2-rc2, v5.2-rc1 |
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4d28ba1d |
| 13-May-2019 |
Leonard Crestez <[email protected]> |
cpufreq: Add imx-cpufreq-dt driver
Right now in upstream imx8m cpufreq support just lists a common subset of OPPs because the higher ones should only be attempted after checking speed grading in fus
cpufreq: Add imx-cpufreq-dt driver
Right now in upstream imx8m cpufreq support just lists a common subset of OPPs because the higher ones should only be attempted after checking speed grading in fuses.
Add a small driver which checks speed grading from nvmem cells before registering cpufreq-dt.
This driver allows unlocking all frequencies for imx8mm and imx8mq and could be applied to other chips like imx7d
Signed-off-by: Leonard Crestez <[email protected]> Signed-off-by: Viresh Kumar <[email protected]>
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Revision tags: v5.1, v5.1-rc7, v5.1-rc6, v5.1-rc5, v5.1-rc4, v5.1-rc3, v5.1-rc2, v5.1-rc1, v5.0, v5.0-rc8, v5.0-rc7, v5.0-rc6, v5.0-rc5, v5.0-rc4, v5.0-rc3 |
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f525a670 |
| 18-Jan-2019 |
Gregory CLEMENT <[email protected]> |
cpufreq: ap806: add cpufreq driver for Armada 8K
Add cpufreq driver for Marvell AP-806 found on Aramda 8K. The AP-806 has DFS (Dynamic Frequency Scaling) with coupled clock domain for two clusters,
cpufreq: ap806: add cpufreq driver for Armada 8K
Add cpufreq driver for Marvell AP-806 found on Aramda 8K. The AP-806 has DFS (Dynamic Frequency Scaling) with coupled clock domain for two clusters, so this driver will directly use generic cpufreq-dt driver as backend.
Based on the work of Omri Itach <[email protected]>.
Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Viresh Kumar <[email protected]>
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Revision tags: v5.0-rc2, v5.0-rc1, v4.20, v4.20-rc7 |
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2849dd8b |
| 14-Dec-2018 |
Taniya Das <[email protected]> |
cpufreq: qcom-hw: Add support for QCOM cpufreq HW driver
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary for changing the frequency of CPUs. The driver implements the cpufr
cpufreq: qcom-hw: Add support for QCOM cpufreq HW driver
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary for changing the frequency of CPUs. The driver implements the cpufreq driver interface for this hardware engine.
Signed-off-by: Saravana Kannan <[email protected]> Signed-off-by: Taniya Das <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Tested-by: Stephen Boyd <[email protected]> Acked-by: Viresh Kumar <[email protected]> Tested-by: Amit Kucheria <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
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