clocksource/drivers/ralink: Add Ralink System Tick Counter driver

System Tick Counter is present on Ralink SoCs RT3352 and MT7620. This
driver has been in 'arch/mips/ralink' directory since the begg

clocksource/drivers/ralink: Add Ralink System Tick Counter driver

System Tick Counter is present on Ralink SoCs RT3352 and MT7620. This
driver has been in 'arch/mips/ralink' directory since the beggining of
Ralink architecture support. However, it can be moved into a more proper
place in 'drivers/clocksource'. Hence add it here adding also support for
compile test targets and reducing LOC in architecture code folder.

Signed-off-by: Sergio Paracuellos <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Daniel Lezcano <[email protected]>

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clocksource/drivers/realtek: Add timer driver for rtl-otto platforms

The timer/counter block on the Realtek SoCs provides up to 5 timers. It
also includes a watchdog timer which is handled by the
re

clocksource/drivers/realtek: Add timer driver for rtl-otto platforms

The timer/counter block on the Realtek SoCs provides up to 5 timers. It
also includes a watchdog timer which is handled by the
realtek_otto_wdt.c driver.

One timer will be used per CPU as a local clock event generator. An
additional timer will be used as an overal stable clocksource.

Signed-off-by: Markus Stockhausen <[email protected]>
Signed-off-by: Sander Vanheule <[email protected]>
Signed-off-by: Chris Packham <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Daniel Lezcano <[email protected]>

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clocksource: ep93xx: Add driver for Cirrus Logic EP93xx

Rewrite EP93xx timer driver located in arch/arm/mach-ep93xx/timer-ep93xx.c
trying to do everything the device tree way:

- Make every IO-acces

clocksource: ep93xx: Add driver for Cirrus Logic EP93xx

Rewrite EP93xx timer driver located in arch/arm/mach-ep93xx/timer-ep93xx.c
trying to do everything the device tree way:

- Make every IO-access relative to a base address and dynamic
so we can do a dynamic ioremap and get going.
- Find register range and interrupt from the device tree.

Reviewed-by: Linus Walleij <[email protected]>
Tested-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Nikita Shubin <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clocksource/drivers/timer-oxnas-rps: Remove obsolete timer driver

Due to lack of maintenance and stall of development for a few years now,
and since no new features will ever be added upstream, remo

clocksource/drivers/timer-oxnas-rps: Remove obsolete timer driver

Due to lack of maintenance and stall of development for a few years now,
and since no new features will ever be added upstream, remove support
for OX810 and OX820 timer.

Acked-by: Linus Walleij <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Daniel Golle <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Acked-by: Andy Shevchenko <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/20230630-topic-oxnas-upstream-remove-v2-3-fb6ab3dea87c@linaro.org

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clocksource/drivers/loongson1: Move PWM timer to clocksource framework

This patch moves most part of arch/mips/loongson32/common/time.c
into drivers/clocksource.

Adapt the driver to clocksource fra

clocksource/drivers/loongson1: Move PWM timer to clocksource framework

This patch moves most part of arch/mips/loongson32/common/time.c
into drivers/clocksource.

Adapt the driver to clocksource framework with devicetree support
and updates Kconfig/Makefile options.

Signed-off-by: Keguang Zhang <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clocksource/drivers/timer-mediatek: Split out CPUXGPT timers

On MediaTek platforms, CPUXGPT is the source for the AArch64 System
Timer, read through CNTVCT_EL0.

The handling for starting this timer

clocksource/drivers/timer-mediatek: Split out CPUXGPT timers

On MediaTek platforms, CPUXGPT is the source for the AArch64 System
Timer, read through CNTVCT_EL0.

The handling for starting this timer ASAP was introduced in commit
327e93cf9a59 ("clocksource/drivers/timer-mediatek: Implement CPUXGPT timers")
which description also contains an important full explanation of the
reasons why this driver is necessary and cannot be a module.

In preparation for an eventual conversion of timer-mediatek to a
platform_driver that would be possibly built as a module, split out
the CPUXGPT timers driver to a new timer-mediatek-cpux.c driver.

This commit brings no functional changes.

Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Walter Chang <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clocksource/drivers/timer-ti-dm: Make timer selectable for ARCH_K3

Let's make timer-ti-dm selectable for ARCH_K3, and add a separate option
for OMAP_DM_SYSTIMER as there should be no need for it on

clocksource/drivers/timer-ti-dm: Make timer selectable for ARCH_K3

Let's make timer-ti-dm selectable for ARCH_K3, and add a separate option
for OMAP_DM_SYSTIMER as there should be no need for it on ARCH_K3.

For older TI SoCs, we are already selecting OMAP_DM_TIMER in
arch/arm/mach-omap*/Kconfig. For mach-omap2, we need to now also select
OMAP_DM_SYSTIMER.

Cc: Keerthy <[email protected]>
Cc: Nishanth Menon <[email protected]>
Cc: Vignesh Raghavendra <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Daniel Lezcano <[email protected]>

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clocksource: Add Tegra186 timers support

Currently this only supports a single watchdog, which uses a timer in
the background for countdown. Eventually the timers could be used for
various time-keep

clocksource: Add Tegra186 timers support

Currently this only supports a single watchdog, which uses a timer in
the background for countdown. Eventually the timers could be used for
various time-keeping tasks, but by default the architected timer will
already provide that functionality.

Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Kartik <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Daniel Lezcano <[email protected]>

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clocksource/drivers/timer-gxp: Add HPE GXP Timer

Add support for the HPE GXP SOC timer. The GXP supports several different
kinds of timers but for the purpose of this driver there is only support
fo

clocksource/drivers/timer-gxp: Add HPE GXP Timer

Add support for the HPE GXP SOC timer. The GXP supports several different
kinds of timers but for the purpose of this driver there is only support
for the General Timer. The timer has a 1us resolution and is 32 bits. The
timer also creates a child watchdog device as the register region is the
same.

Signed-off-by: Nick Hawkins <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>

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clocksource/drivers: Add a goldfish-timer clocksource

Add a clocksource based on the goldfish-rtc device.

Move the timer register definition to <clocksource/timer-goldfish.h>

This kernel implement

clocksource/drivers: Add a goldfish-timer clocksource

Add a clocksource based on the goldfish-rtc device.

Move the timer register definition to <clocksource/timer-goldfish.h>

This kernel implementation is based on the QEMU upstream implementation:

https://git.qemu.org/?p=qemu.git;a=blob_plain;f=hw/rtc/goldfish_rtc.c

goldfish-timer is a high-precision signed 64-bit nanosecond timer.
It is part of the 'goldfish' virtual hardware platform used to run
some emulated Android systems under QEMU.
This timer only supports oneshot event.

Signed-off-by: Laurent Vivier <[email protected]>
Acked-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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remove the h8300 architecture

Signed-off-by: Christoph Hellwig <[email protected]>

nds32: Remove the architecture

The nds32 architecture, also known as AndeStar V3, is a custom 32-bit
RISC target designed by Andes Technologies. Support was added to the
kernel in 2016 as the replac

nds32: Remove the architecture

The nds32 architecture, also known as AndeStar V3, is a custom 32-bit
RISC target designed by Andes Technologies. Support was added to the
kernel in 2016 as the replacement RISC-V based V5 processors were
already announced, and maintained by (current or former) Andes
employees.

As explained by Alan Kao, new customers are now all using RISC-V,
and all known nds32 users are already on longterm stable kernels
provided by Andes, with no development work going into mainline
support any more.

While the port is still in a reasonably good shape, it only gets
worse over time without active maintainers, so it seems best
to remove it before it becomes unusable. As always, if it turns
out that there are mainline users after all, and they volunteer
to maintain the port in the future, the removal can be reverted.

Link: https://lore.kernel.org/linux-mm/[email protected]/
Link: https://lore.kernel.org/lkml/[email protected]/
Link: https://www.andestech.com/en/products-solutions/andestar-architecture/
Signed-off-by: Alan Kao <[email protected]>
[arnd: rewrite changelog to provide more background]
Signed-off-by: Arnd Bergmann <[email protected]>

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clocksource/drivers: Add MStar MSC313e timer support

The MSC313e-compatible SoCs have 3 timer hardware blocks. All of these
are free running 32-bit increasing counters and can generate interrupts.
B

clocksource/drivers: Add MStar MSC313e timer support

The MSC313e-compatible SoCs have 3 timer hardware blocks. All of these
are free running 32-bit increasing counters and can generate interrupts.
Based onto a maximum value register, each timer can either count from 0
to max, one time then stop (which generates interrupts) or can count
from 0 to max and then roll. This commit adds basic support for these
timers, the first timer block being used as clocksource/sched_clock
and delay, while the others will be used as clockevents.

Signed-off-by: Romain Perier <[email protected]>
Co-developed-by: Daniel Palmer <[email protected]>
Signed-off-by: Daniel Palmer <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Daniel Lezcano <[email protected]>

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clocksource/drivers/prima: Remove sirf prima driver

The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.

Cc: Barry Song <[email protected]>
Signed-off-by: Ar

clocksource/drivers/prima: Remove sirf prima driver

The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.

Cc: Barry Song <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
Acked-by: Barry Song <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clocksource/drivers/atlas: Remove sirf atlas driver

The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.

Cc: Barry Song <[email protected]>
Signed-off-by: Ar

clocksource/drivers/atlas: Remove sirf atlas driver

The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.

Cc: Barry Song <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
Acked-by: Barry Song <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clocksource/drivers/tango: Remove tango driver

The tango platform is getting removed, so the driver is no
longer needed.

Cc: Marc Gonzalez <[email protected]>
Cc: Mans Rullgard <[email protected]

clocksource/drivers/tango: Remove tango driver

The tango platform is getting removed, so the driver is no
longer needed.

Cc: Marc Gonzalez <[email protected]>
Cc: Mans Rullgard <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
Acked-by: Mans Rullgard <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clocksource/drivers/u300: Remove the u300 driver

The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.

Cc: Linus Walleij <[email protected]>
Signed-off-by: Ar

clocksource/drivers/u300: Remove the u300 driver

The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.

Cc: Linus Walleij <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clocksource/drivers/efm32: Drop unused timer code

Support for this machine was just removed, so drop the now unused timer
code, too.

Signed-off-by: Uwe Kleine-König <[email protected]>

clocksource/drivers/efm32: Drop unused timer code

Support for this machine was just removed, so drop the now unused timer
code, too.

Signed-off-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clocksource/drivers/nps: Remove EZChip NPS clocksource driver

NPS platform has been removed from ARC port and there are no in-tree
users of it now. So RIP !

Cc: Daniel Lezcano <daniel.lezcano@linar

clocksource/drivers/nps: Remove EZChip NPS clocksource driver

NPS platform has been removed from ARC port and there are no in-tree
users of it now. So RIP !

Cc: Daniel Lezcano <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Signed-off-by: Vineet Gupta <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clocksource/drivers: Add CLINT timer driver

We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e.
RISC-V NoMMU kernel).

The CLINT MMIO device provides three things:
1. 64bit free runni

clocksource/drivers: Add CLINT timer driver

We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e.
RISC-V NoMMU kernel).

The CLINT MMIO device provides three things:
1. 64bit free running counter register
2. 64bit per-CPU time compare registers
3. 32bit per-CPU inter-processor interrupt registers

Unlike other timer devices, CLINT provides IPI registers along with
timer registers. To use CLINT IPI registers, the CLINT timer driver
provides IPI related callbacks to arch/riscv.

Signed-off-by: Anup Patel <[email protected]>
Tested-by: Emil Renner Berhing <[email protected]>
Acked-by: Daniel Lezcano <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Palmer Dabbelt <[email protected]>

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clocksource/drivers/ingenic: Add support for the Ingenic X1000 OST.

X1000 and SoCs after X1000 (such as X1500 and X1830) had a separate
OST, it no longer belongs to TCU. This driver will register bo

clocksource/drivers/ingenic: Add support for the Ingenic X1000 OST.

X1000 and SoCs after X1000 (such as X1500 and X1830) had a separate
OST, it no longer belongs to TCU. This driver will register both a
clocksource and a sched_clock to the system.

Tested-by: 周正 (Zhou Zheng) <[email protected]>
Co-developed-by: 漆鹏振 (Qi Pengzhen) <[email protected]>
Signed-off-by: 漆鹏振 (Qi Pengzhen) <[email protected]>
Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]>
Reviewed-by: Paul Cercueil <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clocksource: Add Low Power STM32 timers driver

Implement clock event driver using low power STM32 timers.
Low power timer counters running even when CPUs are stopped.
It could be used as clock event

clocksource: Add Low Power STM32 timers driver

Implement clock event driver using low power STM32 timers.
Low power timer counters running even when CPUs are stopped.
It could be used as clock event broadcaster to wake up CPUs but not like
a clocksource because each it rise an interrupt the counter restart from 0.

Low power timers have a 16 bits counter and a prescaler which allow to
divide the clock per power of 2 to up 128 to target a 32KHz rate.

Signed-off-by: Benjamin Gaignard <[email protected]>
Signed-off-by: Pascal Paillet <[email protected]>
Acked-by: Daniel Lezcano <[email protected]>
Signed-off-by: Lee Jones <[email protected]>

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clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support

We can move the TI dmtimer clockevent and clocksource to live under
drivers/clocksource if we rely only on the clock framework

clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support

We can move the TI dmtimer clockevent and clocksource to live under
drivers/clocksource if we rely only on the clock framework, and handle
the module configuration directly in the clocksource driver based on the
device tree data.

This removes the early dependency with system timers to the interconnect
related code, and we can probe pretty much everything else later on at
the module_init level.

Let's first add a new driver for timer-ti-dm-systimer based on existing
arch/arm/mach-omap2/timer.c. Then let's start moving SoCs to probe with
device tree data while still keeping the old timer.c. And eventually we
can just drop the old timer.c.

Let's take the opportunity to switch to use readl/writel as pointed out
by Daniel Lezcano <[email protected]>. This allows further
clean-up of the timer-ti-dm code the a lot of the shared helpers can
just become static to the non-syster related code.

Note the boards can optionally configure different timer source clocks
if needed with assigned-clocks and assigned-clock-parents.

Cc: [email protected]
Cc: [email protected]
Cc: Daniel Lezcano <[email protected]>
Cc: Grygorii Strashko <[email protected]>
Cc: Keerthy <[email protected]>
Cc: Lokesh Vutla <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Tero Kristo <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support

We can move the TI dmtimer clockevent and clocksource to live under
drivers/clocksource if we rely only on the clock framework

clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support

We can move the TI dmtimer clockevent and clocksource to live under
drivers/clocksource if we rely only on the clock framework, and handle
the module configuration directly in the clocksource driver based on the
device tree data.

This removes the early dependency with system timers to the interconnect
related code, and we can probe pretty much everything else later on at
the module_init level.

Let's first add a new driver for timer-ti-dm-systimer based on existing
arch/arm/mach-omap2/timer.c. Then let's start moving SoCs to probe with
device tree data while still keeping the old timer.c. And eventually we
can just drop the old timer.c.

Let's take the opportunity to switch to use readl/writel as pointed out
by Daniel Lezcano <[email protected]>. This allows further
clean-up of the timer-ti-dm code the a lot of the shared helpers can
just become static to the non-syster related code.

Note the boards can optionally configure different timer source clocks
if needed with assigned-clocks and assigned-clock-parents.

Cc: [email protected]
Cc: [email protected]
Cc: Daniel Lezcano <[email protected]>
Cc: Grygorii Strashko <[email protected]>
Cc: Keerthy <[email protected]>
Cc: Lokesh Vutla <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Tero Kristo <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clocksource: Add driver for the Ingenic JZ47xx OST

OST is the OS Timer, a 64-bit timer/counter with buffered reading.

SoCs before the JZ4770 had (if any) a 32-bit OST; the JZ4770 and
JZ4780 have a

clocksource: Add driver for the Ingenic JZ47xx OST

OST is the OS Timer, a 64-bit timer/counter with buffered reading.

SoCs before the JZ4770 had (if any) a 32-bit OST; the JZ4770 and
JZ4780 have a 64-bit OST.

This driver will register both a clocksource and a sched_clock to the
system.

Signed-off-by: Maarten ter Huurne <[email protected]>
Signed-off-by: Paul Cercueil <[email protected]>
Tested-by: Mathieu Malaterre <[email protected]>
Tested-by: Artur Rojek <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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