clk: renesas: rzv2h: Add support for RZ/G3E SoC

The clock structure for RZ/G3E is almost identical to RZ/V2H SoC with
more IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1
are present

clk: renesas: rzv2h: Add support for RZ/G3E SoC

The clock structure for RZ/G3E is almost identical to RZ/V2H SoC with
more IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1
are present only on the RZ/G3E SoC.

Add minimal clock and reset entries required to boot the Renesas RZ/G3E
SMARC EVK and binds it with the RZ/V2H CPG core driver.

Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: vbattb: Add VBATTB clock driver

The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used
by the RTC. The input to the VBATTB could be a 32KHz crystal
or an external cloc

clk: renesas: vbattb: Add VBATTB clock driver

The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used
by the RTC. The input to the VBATTB could be a 32KHz crystal
or an external clock device.

The HW block diagram for the clock generator is as follows:

+----------+ XC `\
RTXIN --->| |----->| \ +----+ VBATTCLK
| 32K clock| | |----->|gate|----------->
| osc | XBYP | | +----+
RTXOUT --->| |----->| /
+----------+ ,

After discussions w/ Stephen Boyd the clock tree associated with this
hardware block was exported in Linux as:

vbattb-xtal
xbyp
xc
mux
vbattbclk

where:
- input-xtal is the input clock (connected to RTXIN, RTXOUT pins)
- xc, xbyp are mux inputs
- mux is the internal mux
- vbattclk is the gate clock that feeds in the end the RTC

to allow selecting the input of the MUX though assigned-clock DT
properties, using the already existing clock drivers and avoid adding
other DT properties. If the crystal is connected on RTXIN,
RTXOUT pins the XC will be selected as mux input. If an external clock
device is connected on RTXIN, RTXOUT pins the XBYP will be selected as
mux input.

The load capacitance of the internal crystal can be configured
with renesas,vbattb-load-nanofarads DT property.

Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: Add RZ/V2H(P) CPG driver

Add RZ/V2H(P) CPG driver.

Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Lin

clk: renesas: Add RZ/V2H(P) CPG driver

Add RZ/V2H(P) CPG driver.

Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: Add family-specific clock driver for RZ/V2H(P)

Add family-specific clock driver for RZ/V2H(P) SoCs.

Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by:

clk: renesas: Add family-specific clock driver for RZ/V2H(P)

Add family-specific clock driver for RZ/V2H(P) SoCs.

Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: Drop "Renesas" from individual driver descriptions

All configuration options are under the big "Renesas SoC clock support"
umbrella, so there is no reason to repeat this for each drive

clk: renesas: Drop "Renesas" from individual driver descriptions

All configuration options are under the big "Renesas SoC clock support"
umbrella, so there is no reason to repeat this for each driver.
Hence drop "Renesas" from the few that do.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/185323de4d38b9b599775c1b64ce4171551b98d5.1718177124.git.geert+renesas@glider.be

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clk: renesas: cpg-mssr: Add support for R-Car V4M

Initial CPG support for the R-Car V4M (R8A779H0).

Signed-off-by: Cong Dang <[email protected]>
Signed-off-by: Geert Uytterhoeven <geert+rene

clk: renesas: cpg-mssr: Add support for R-Car V4M

Initial CPG support for the R-Car V4M (R8A779H0).

Signed-off-by: Cong Dang <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Niklas Söderlund <[email protected]>
Link: https://lore.kernel.org/r/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be

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clk: renesas: Add minimal boot support for RZ/G3S SoC

Add minimal clock and reset support for the RZ/G3S SoC to be able to
boot Linux from SD Card/eMMC. This includes necessary core clocks for
boot

clk: renesas: Add minimal boot support for RZ/G3S SoC

Add minimal clock and reset support for the RZ/G3S SoC to be able to
boot Linux from SD Card/eMMC. This includes necessary core clocks for
booting and GIC, SCIF, GPIO, and SD0 module clocks and resets.

Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*

R-Car H3 ES1.* was only available to an internal development group and
needed a lot of quirks and workarounds. These become a maintenance
burden now,

clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*

R-Car H3 ES1.* was only available to an internal development group and
needed a lot of quirks and workarounds. These become a maintenance
burden now, so our development group decided to remove upstream support
for this SoC. Public users only have ES2 onwards.

In addition to the ES1 specific removals, a check for it was added
preventing the machine to boot further. It may otherwise inherit wrong
clock settings from ES2 which could damage the hardware.

Signed-off-by: Wolfram Sang <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: Add RZ/V2M support using the rzg2l driver

The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have
any CLK_MON registers.

Signed-off-by: Phil Edworthy <phil.edworthy@r

clk: renesas: Add RZ/V2M support using the rzg2l driver

The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have
any CLK_MON registers.

Signed-off-by: Phil Edworthy <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: cpg-mssr: Add support for R-Car V4H

Initial CPG support for R-Car V4H (r8a779g0).

Signed-off-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/2

clk: renesas: cpg-mssr: Add support for R-Car V4H

Initial CPG support for R-Car V4H (r8a779g0).

Signed-off-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: Add support for RZ/G2UL SoC

The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with
fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are
not present

clk: renesas: Add support for RZ/G2UL SoC

The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with
fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are
not present on RZ/G2UL.

This patch adds minimal clock and reset entries required to boot the
system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core
driver.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC

The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC.
The only difference being that RZ/V2L has additional registers to
control cl

clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC

The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC.
The only difference being that RZ/V2L has additional registers to
control clocks and resets for the DRP-AI block.

Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same
between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take
care of the DRP-AI clocks/resets.

Signed-off-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: cpg-mssr: Add support for R-Car S4-8

Initial CPG support for R-Car S4-8 (r8a779f0).

Inspired by patches in the BSP by LUU HOAI.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh

clk: renesas: cpg-mssr: Add support for R-Car S4-8

Initial CPG support for R-Car S4-8 (r8a779f0).

Inspired by patches in the BSP by LUU HOAI.

Signed-off-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver

According to the official website [1], the R-Car V3U SoC is based
on the R-Car Gen4 architecture. So, introduce R-Car Gen4 CPG
driver.

[1]
h

clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver

According to the official website [1], the R-Car V3U SoC is based
on the R-Car Gen4 architecture. So, introduce R-Car Gen4 CPG
driver.

[1]
https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-driving

Signed-off-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: Make CLK_R9A06G032 invisible

When configuring a kernel including support for Renesas ARM/ARM64 Socs,
but excluding support for the RZ/N1D SoC, the user is always asked about
the RZ/N1D

clk: renesas: Make CLK_R9A06G032 invisible

When configuring a kernel including support for Renesas ARM/ARM64 Socs,
but excluding support for the RZ/N1D SoC, the user is always asked about
the RZ/N1D clock driver. As this driver is already auto-selected when
building a kernel including support for the RZ/N1D SoC, there is no need
to make the CLK_R9A06G032 symbol visible, unless compile-testing.

Align the symbol description with the other symbols.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Niklas Söderlund <[email protected]>
Link: https://lore.kernel.org/r/4f3d30c730c30546f702715ffc648922a8156703.1628672649.git.geert+renesas@glider.be

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clk: renesas: Add support for R9A07G044 SoC

Define the clock outputs supported by RZ/G2L (R9A07G044) SoC
and bind it with RZ/G2L CPG core.

Based on a patch in the BSP by Binh Nguyen
<binh.nguyen.jz

clk: renesas: Add support for R9A07G044 SoC

Define the clock outputs supported by RZ/G2L (R9A07G044) SoC
and bind it with RZ/G2L CPG core.

Based on a patch in the BSP by Binh Nguyen
<[email protected]>.

Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: Add CPG core wrapper for RZ/G2L SoC

Add CPG core wrapper for RZ/G2L family.

Based on a patch in the BSP by Binh Nguyen
<[email protected]>.

Signed-off-by: Lad Prabhakar <pra

clk: renesas: Add CPG core wrapper for RZ/G2L SoC

Add CPG core wrapper for RZ/G2L family.

Based on a patch in the BSP by Binh Nguyen
<[email protected]>.

Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: r8a779a0: Add SDHI support

We use the shiny new CPG library for that.

Signed-off-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/20201227174202.408

clk: renesas: r8a779a0: Add SDHI support

We use the shiny new CPG library for that.

Signed-off-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: rcar-gen3: Factor out CPG library

R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but
similar enough to reuse code. Introduce a new CPG library, factor out
the SD clo

clk: renesas: rcar-gen3: Factor out CPG library

R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but
similar enough to reuse code. Introduce a new CPG library, factor out
the SD clock handling and hook it to the generic Gen3 CPG driver so we
have an equal state. V3U will make use of it in the next patch then.

Signed-off-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: rcar-gen3: Update description for RZ/G2

The rcar-gen3-cpg driver is also used on Renesas RZ/G2 SoC's, update the
description for the CLK_RCAR_GEN3_CPG config symbol to reflect this.

S

clk: renesas: rcar-gen3: Update description for RZ/G2

The rcar-gen3-cpg driver is also used on Renesas RZ/G2 SoC's, update the
description for the CLK_RCAR_GEN3_CPG config symbol to reflect this.

Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Chris Paterson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: cpg-mssr: Add support for R-Car V3U

Initial support for R-Car V3U (r8a779a0), including core, module
clocks, resets, and register access, because register specification
differs from R-

clk: renesas: cpg-mssr: Add support for R-Car V3U

Initial support for R-Car V3U (r8a779a0), including core, module
clocks, resets, and register access, because register specification
differs from R-Car Gen2/3.

Inspired by patches in the BSP by LUU HOAI.

Signed-off-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/1599810232-29035-4-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: cpg-mssr: Add r8a774e1 support

Add support for the RZ/G2H (R8A774E1) SoC to the Renesas Clock
Pulse Generator / Module Standby and Software Reset driver.

Signed-off-by: Marian-Cristia

clk: renesas: cpg-mssr: Add r8a774e1 support

Add support for the RZ/G2H (R8A774E1) SoC to the Renesas Clock
Pulse Generator / Module Standby and Software Reset driver.

Signed-off-by: Marian-Cristian Rotariu <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/1594138692-16816-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
[geert: Mark RWDT critical, cfr. commit f23f1101ad0ef1ac ("clk: renesas: rcar-gen3: Mark RWDT clocks as critical")]
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects

CLK_RENESAS_CPG_MSSR selects CLK_RENESAS_DIV6, and CLK_RCAR_GEN2_CPG
selects CLK_RENESAS_CPG_MSSR, so there is no longer a need f

clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects

CLK_RENESAS_CPG_MSSR selects CLK_RENESAS_DIV6, and CLK_RCAR_GEN2_CPG
selects CLK_RENESAS_CPG_MSSR, so there is no longer a need for the
individual R-Car Gen2 clock driver options to select CLK_RENESAS_DIV6.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Niklas Söderlund <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clk: renesas: cpg-mssr: Add R8A7742 support

Add RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G

clk: renesas: cpg-mssr: Add R8A7742 support

Add RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.

Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Link: https://lore.kernel.org/r/1587998460-7804-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <[email protected]>

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clk: renesas: rcar-usb2-clock-sel: Add reset_control

This hardware needs to deassert resets of both host and peripheral.
So, this patch adds reset control.

Signed-off-by: Yoshihiro Shimoda <yoshihi

clk: renesas: rcar-usb2-clock-sel: Add reset_control

This hardware needs to deassert resets of both host and peripheral.
So, this patch adds reset control.

Signed-off-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/1583304137-28482-5-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <[email protected]>

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